• KSCI Review
• /
• v.2 no.2
• /
• pp.19-26
• /
• 1996

The improvement of word processor has been done rapidly according with generalized acceptance of GUI Environment such as Windows. So in this paper, with the result of analysing the functions of korean word processor on Windows, I will propose the method of enhancement of GUI based word processor and discuss the direction of multimedia word processor.

• Journal of Korean Library and Information Science Society
• /
• v.12
• /
• pp.199-232
• /
• 1985

Word processor having the functions of a typewriter and a computer together have been used as a powerful tools for office automation. The purpose of this study is to find out the possible areas of the word processing a n.0, pplication in the library operations. For the study, the general concept, developmental process, structure, functions, kinds and suggested a n.0, pplicable areas in the library operations of word processor were investigated. Then, the cases of real a n.0, pplications of word processor in the library field were examplified. In conclusion, the areas where word processor can be of benefit to library workers can be summarized as follows, 1) Orders of books and periodical acquisitions, 2) On-line searching, and storage and editing of input as required, 3) Production of catalogues, and abstracting and indexing bulletin, 4) Budget control, circulation control, and serial control.

• Journal of Institute of Control, Robotics and Systems
• /
• v.14 no.10
• /
• pp.1081-1087
• /
• 2008

This paper describes limitations and solutions of the existing processor-monitoring concept for a military supersonics aircraft Flight Control Computer (FLCC) equipped with modern architecture processor to perform the system integration test. Safecritical FLCC integration test, which requires automatic test for thousands of test cases and real-time input/output test condition generation, depends on the processor-monitoring device called Processor Interface (PI). The PI, which relies upon on the FLCC processor's external address and data-bus data, has some limitations due to multi-fetching capability of the modern sophisticated military processors, like C6000's VLIW (Very-Long Instruction Word) architecture and PowerPC's Superscalar architecture. Several techniques for limitations were developed and proper monitoring approach was presented for modem processor-adopted FLCC system integration test.

• Proceedings of the KIEE Conference
• /
• 2002.07d
• /
• pp.2534-2536
• /
• 2002

This paper presents the design of high speed bit and word processor for sequence logic control using a FPGA. This FPGA is able to execute sequence instruction during program fetch cycle, because the program memory was separated from the data memory for high speed execution at 40MHz clock. Also this processor has 274 instructions set with a 32bit fixed width, so instruction decoding time and data memory interface time was reduced. This FPGA was synthesized by V600EHQ240 and Foundation tool of Xilinx company. The final simulation was successfully performed under Foundation tool simulation environment. And the FPGA programmed by VHDL for a 240 pin HQFP package. Finally the benchmark was performed to prove that the designed for bit and word processor has better performance than Q4A of Mitsubishi for the sequence logic control.

• The KIPS Transactions:PartC
• /
• v.14C no.4
• /
• pp.313-320
• /
• 2007

In this paper, we propose a method to analyze security vulnerabilities of MS word-processor by checking the validation of its input files. That is, this study is to detect some vulnerabilities in the input file of the word processor by analyzing the header information of its input file. This validation test can not be conducted by the existing software fault injection tools including Holodeck and CANVAS. The proposed method can be also applied to identify the input file vulnerabilities of Hangul and Microsoft Excel which handle a data file with a header as an input. Moreover, our method can provide a means for assessing the fault tolerance and trustworthiness of the target software.

• Journal of KIISE:Computer Systems and Theory
• /
• v.31 no.5_6
• /
• pp.279-287
• /
• 2004

This paper describes a processor architecture, named Dynamically Instruction Scheduled VLIW (DISVLIW). The DISVLIW Processor architecture is designed for dynamic scheduling VLIW instructions using dependency information. The DISVLIW instruction format is augmented to allow dependency bit vectors to be placed in the same VLIW word. The DISVLIW processor dynamically schedules each instruction in long instructions using functional unit and dynamic scheduler pairs. Features such as explicit parallelism, balanced scheduling effort, and dynamic scheduling of VLIW instructions can be used to provide a sound frustructure for supercomputing. We simulate the DISVLIW processor architecture and show that the DISVLIW processor performs significantly better than the VLIW processor for a wide range of cache sites and across numerical benchmark applications.

• The Transactions of the Korea Information Processing Society
• /
• v.4 no.9
• /
• pp.2269-2279
• /
• 1997

SVLIW (Superscalar VLIW) processor, a family of VLIW processors schedules very long instruction words at runtime. If a very long instruction word that is to be issued occurs data dependence relations and/or resource conflicts with those words that were under execution, a long NOP word is issued instead of the word until all the data dependence relations and/or resource conflicts have been resolved. Thus, LNOPs can be removed in object codes for SVLIW processors. In this paper, we measure an improvement of the cache hit ratio caused by removing LNOPs in the object code. We also analyze an improvement of the processor performance due to higher cache hit ratio of the processor. Benchmark tests promise that the performance of SVLIW processors is improved more than 5% compared with that of traditional VLIW processors.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2013.05a
• /
• pp.613-615
• /
• 2013

Request to provide a service to XML word file recently has been increasing. In this paper, it is converted to an XML file data input (HWP, MS-Office) a Word file, stored in a database by extracting data directly input to the word processor user creates an XML mapping file I to provide a system that. This can be retrieved from the database the required data to previously created forms word processor, to generate a Word file from the application program a word processing document.

• Journal of The Korean Association of Information Education
• /
• v.7 no.1
• /
• pp.37-47
• /
• 2003

A grading system of practical word processor skills is designed and implemented by using HWPML(Hangul Word Processor Markup Language) which is a product of Hangul and Computer Co Ltd. By using HWPML, which is a markup tag structure of Hangul file, Hangul files can be edited in other application programs. Authorized users can make questions. However, only the manager is allowed to register answers to the questions in order to maintain the correctness of grading. The result of test is stored in the database and the statistics on pass or failure can be shown interactively. The number of taking test and scores for each user are stored in the database and they can be accessed to whenever the user wants them. Comments on the test results are provided by the manager so that learners can intensity their weak points.

• 제어로봇시스템학회:학술대회논문집
• /
• 1993.10a
• /
• pp.1012-1017
• /
• 1993

In this paper, the instruction set and the architecture of a RISC processor for programmable logic controller is suggested. From the measurement of existing programs, the characteristics of ladder instructions are analyzed. The instruction set is defined so that the existing ladder program can be reused with simple translation. Because bit instructions controls the behavior of word instructions, the processor suits for high level language like SFC. Simulations show that the PLC with the suggested processor is twenty times faster than the PLC with the multi-purpose microprocessor.