Journal of KIISE:Computer Systems and Theory (한국정보과학회논문지:시스템및이론)

Korean Institute of Information Scientists and Engineers (한국정보과학회)
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Compiler Processor Trade-offs for Dynamic Scheduling of VLIW Instructions

VLIW명령어의 동적 스케줄링을 위한 컴파일러와 프로세서간 상호보완

  • Published : 2004.06.01
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Abstract

This paper describes a processor architecture, named Dynamically Instruction Scheduled VLIW (DISVLIW). The DISVLIW Processor architecture is designed for dynamic scheduling VLIW instructions using dependency information. The DISVLIW instruction format is augmented to allow dependency bit vectors to be placed in the same VLIW word. The DISVLIW processor dynamically schedules each instruction in long instructions using functional unit and dynamic scheduler pairs. Features such as explicit parallelism, balanced scheduling effort, and dynamic scheduling of VLIW instructions can be used to provide a sound frustructure for supercomputing. We simulate the DISVLIW processor architecture and show that the DISVLIW processor performs significantly better than the VLIW processor for a wide range of cache sites and across numerical benchmark applications.

본 논문에서 제안한 DISVLIW(Dynamically Instruction Scheduled VLIW) 프로세서 구조는 자료종속성 정보를 이용하여 VLIW(Very Long Instruction Word) 명령어들을 동적으로 스케줄링 할 수 있다. 이러한 동작을 수행하기 위해서, DISVLIW 프로세서는 연산처리기와 동적 스케줄러의 쌍들로 구성되었다. VLIW 명령어들의 동적 스케줄링, 컴파일시간과 실시간의 균등한 작업분배, 명령어내의 명백한 병렬성 표현 둥의 특징은 성능향상에 중요한 영향을 미쳤다. DISVLIW 프로세서 구조의 시뮬레이션 결과, 다양한 벤치마크들과 캐쉬메모리 사이즈들을 이용할 경우에도 DISVLIW 프로세서 구조가 VLIW 프로세서 구조에 비하여 항상 높은 성능향상을 가짐을 확인하였다.

Keywords

References

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