• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.7-14
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• 2017

Due to the recent advances in Phage-Change Memory (PCM) technologies, a new memory hierarchy of computer systems with PCM is expected to appear. In this paper, we present a new page replacement policy that adopts PCM as a high speed swap device. As PCM has limited write endurance, our goal is to minimize the amount of data written to PCM. To do so, we defer the eviction of dirty pages in proportion to their dirtiness. However, excessive preservation of dirty pages in memory may deteriorate the page fault rate, especially when the memory capacity is not enough to accommodate full working-set pages. Thus, our policy monitors the current working-set size of the system, and controls the deferring level of dirty pages not to degrade the system performances. Simulation experiments show that the proposed policy reduces the write traffic to PCM by 160% without performance degradations.

• Proceedings of the Korean Information Science Society Conference
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• 1999.10c
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• pp.399-401
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• 1999

최근 컴퓨터 네트워크를 통한 화상회의, 화상전화 VOD 등과 같은 응용 프로그램들이 실시간 통신을 필요로 한다. 이러한 실시간 통신에 적합한 ATM은 유연한 통신 서비스와 높은 질의 서비스를 제공함으로서 차세대 통신 네트웍으로 기대가 되고 있다. ATM 네트웍 막에서 실시간 통신을 하기 위해서는 실시간 데이터들이 지연한계를 만족해야 한다. 만약 이러한 지연한계를 만족시키지 못할 경우에는 서비스의 질이 떨어지거나 아니면 데이터가 아예 필요가 없어지게 된다. 이미 실시간 통신을 하기 위해 Virtual Clock, Stop-and-Go, EDF 등에 많은 패킷 스위치 스케줄링 정책들이 개발 되어져 왔다. 그러나 이러한 스위치 스케줄링 정책들은 대부분 그 방법의 복잡성 때문에 실제로 ATM 상에서 적용시키기가 힘들다. 본 논문에서는 ATM 네트웍 망에서 화상 통신을 하기 위해 적합한 새로운 스위치 모델인 TCRM-DS를 제시한다. TCRM-DS는 기존의 TCRM 모델의 장점인 단순성과 효율성을 그대로 유지하면서 TCRM 모델의 단점인 비 실시간 데이터에 대한 비효율적 처리를 개선한 것이다.

• Proceedings of the Korea Society for Simulation Conference
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• 1998.10a
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• pp.66-70
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• 1998

제조환경 정보의 급속한 변화는 변화에 유연(flexible)하게 대처할 수 있는 제조관리 시스템 개발을 요구하게 되었으며 이를 위한 방법으로 객체지향 개발방법론을 이용한 제조관리 시스템이 구축되어 시스템 구성요소들의 재사용성, 확장성, 유연성을 높일 수 있게 되었다. 그러나 개발된 객체지향 제조관리 시스템은 과거 데이터와 불확실한 데이터를 바탕으로 개발된 시스템이므로 시스템의 타당성 및 효율성의 검증을 위한 방법으로 객체지향 시뮬레이터를 개발하였다. 객체지향 시뮬레이터는 개발된 제조관리 시스템이 현장에 구축되었을 때 발생될 수 있는 문제점을 사전에 검출할 수 있을 뿐만 아니라 시스템의 성능을 사전에 측정할 수 있어 제조관리 시스템의 개발비용을 단축할 수 있게 된다. 본 연구에서는 가상공장의 특성을 구현한 가상공장(virtual factory) 콤포넌트, 제조관리 시스템과의 인터페이스를 담당하는 커넥터(connector) 콤포넌트, 제조시스템의 구성환경을 모델링하는 컨피규레이션(configuration) 콤포넌트, 시뮬레이션의 시간전진을 담당하는 시계(clock) 콤포넌트 등으로 이루어진 객체지향 시뮬레이션의 프레임워크(framework)를 제시하고, 제조관리 시스템과 연계된 시뮬레이션을 통해 제조관리 시스템의 검증, 평가 방안으로 이용하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.4
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• pp.344-350
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• 2011

Higher integrated density in 3D ICs also brings the difficulties of routing, which can cause the routing failure or re-design from beginning. Hence, precise congestion estimation at the early physical design stage such as floorplan is beneficial to reduce the total design time cost. In this paper, an effective estimation method of routing congestion is proposed for 3D ICs at floorplan stage. This method uses synthesized virtual signal nets, power/ground network and clock network to achieve the estimation. During the synthesis, the TSV location is also under consideration. The experiments indicate that our proposed method had small difference with the estimation result got at the post-placement stage. Furthermore, the comparison of congestion maps obtained with our method and global router demonstrates that our estimation method is able to predict the congestion hot spots accurately.

• Journal of Electrical Engineering and information Science
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• v.2 no.6
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• pp.74-81
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• 1997

Xcent-Net is a new system network designed to support a clustered SMP called SPAX(Scalable Parallel Architecture based on Xbar) that is being developed by ETRI. It is a duplicated hierarchical crossbar network to provide the connections among 16 clusters of 128 nodes. Xcent-Net is designed as a packet switched, virtual cut-through routed, point-to-point network. Variable length packets contain up to 64 bytes of data. The packets are transmitted via full duplexed, 32-bit wide channels using source synchronous transmission technique. Its plesiochronous clocking scheme eliminates the global clock distribution problem. Two level priority-based round-robin scheme is adopted to resolve the traffic congestion. Clear-to-send mechanism is used as a packet level flow control scheme. Most of functions are built in Xcent router, which is implemented as an ASIC. This paper describes the architecture and the functional features of Xcent-Net and discusses its implementation.

• Proceedings of the Korean Information Science Society Conference
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• 2006.10a
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• pp.176-180
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• 2006

이 논문에서는, 과거의 사용량 정보와 서비스 지연시간이 상호 의존관계를 가지는 지연시간-대역폭 정규화 개념을 설명하고, 이에 기반한 스펙트럼 형태의 스케줄링 모델을 제시한다. 이 모델에서는 각 응용이 자원을 획득할 수 있는 권한을 주기적으로 축적하며, 서비스를 받을 경우 그 권한을 소비하게 된다. 사용되지 않고 축적된 권한은 추후의 스케줄링에서 자원 획득 가능성을 높여 지연시간을 단축시키는 효과를 낸다. 이 때 과거의 축적된 정보를 주기적으로 감쇄시킴으로써 과거의 사용 정보를 부분적으로 망각하도록 할 수 있으며, 그 감쇄 정도에 따라 지연시간-대역폭 정규화 정도를 제어할 수 있다. 이 기본적 모델의 세부사항을 조절함으로써 이 모델이 GPS, virtual clock, decay usage 등의 스케줄러와 유사한 특성을 나타낼 수 있음을 보였으며, 이를 통해 기존의 무관해 보이는 스케줄러들이 연속적인 스펙트럼상에 존재함을 설명하였다. 또한 시뮬레이션을 통해 모델의 특성을 관찰하였다.

• Journal of the Korea Society for Simulation
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• v.7 no.1
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• pp.15-26
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• 1998

In building a shell-based FMS, which is known as one of the top-down approaches in the field of factory automation, we may take a hybrid simulation into consideration. The modeling of a hybrid simulation consists of real physical entities, virtual simulation, and central clock algorithm, etc. to carry out the whole system operation. In this paper, we sow a way to construct a hybrid simulation software system in manufacturing environments. We bring in the object-oriented methodology in system design and it can contribute in dealing with a wide variety of production types and configurations. Some classes such as project, product, process, order, schedule, stage are defined. These are used and tested by implementing a specific LSI circuit assembly line process.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.1
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• pp.1-8
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• 1999

In order to provide appropriate Quality of Service(QoS) guarantee to each traffic flow in intergrated service networks, an efficient traffic scheduling algorithm as well as resource reservation must be adopted in host and transit routers. In this paper, a new efficient fair queueing algorithm which adopts a linearly increasing virtual time is presented. The proposed algorithm is fair and the maximum and mean delay guaranteed of each flow are less than those of the SCFQ(self clocked fair queueing) algorithm which is one of the most promising traffic scheduling algorithm, while providing low implementation complexity as the SCFQ scheme. And, it has the better isolation provided than SCFQ, which means that each flow is much less influenced by the violating traffic flows provided its allocated bandwidth gurantee. The fairness of the proposed algorithm is proved and simulation results of maximum and mean delay presented.

• KIPS Transactions on Computer and Communication Systems
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• v.5 no.11
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• pp.393-402
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• 2016

A Military L-V-C system consists of distributed complex systems integrating Live systems working on physical wall-clock time, Virtual systems ruled by virtually pseudo realtime events on a computer, and Constructive systems only depending on the causal relationship between the continuous events. Recently many needs for L-V-C training systems are increasing in order to achieve the maximum training effects with low costs. While theoretical/logical researches or only partially interworking technologies have been proposed, there are few perfect interworking architectures for totally interoperating L-V-C systems in world-wide. In this paper, we design and develop a novel interworking architecture based on data centric middleware for the consistent global time with the same states on the entire L-V-C data and events by means of integrating the heterogeneous distributed middleware standards of each L-V-C system. In addition, simulated L-V-C systems based on real systems will be used for the efficiency and performance of the developed interworking architecture.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.22 no.6
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• pp.57-62
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• 2022

Recently, fast storage media such as phage-change memory (PCM) emerge, and memory management policies for slow disk storage need to be revisited. In this paper, we propose a new page replacement policy that makes use of PCM as a swap device of virtual memory systems. The proposed policy aims at reducing write traffic to the swap device as well as reducing the number of page faults pursued by traditional page replacement policies. This is because a write operation in PCM is slow and PCM has limited write endurances. Specifically, the proposed policy focuses on the reduction of page faults when the memory load of the system is high, but it aims at reducing write traffic to storage when free memory space is sufficient. Simulation experiments with various memory reference traces show that the proposed policy reduces write traffic to PCM without performance degradations.