• Journal of IKEEE
• /
• v.26 no.2
• /
• pp.313-318
• /
• 2022

The feedback voltage detection structure is proposed to alleviate overshoot and undershoot caused by the removal of the existing external output capacitor. Conventional LDO regulators suffer from overshoot and undershoot caused by imbalances in the power supply voltage. Therefore, the proposed LDO is designed to have a more improved transient response to form a new control path while maintaining only the feedback path of the conventional LDO regulator. A new control path detects overshoot and undershoot events in the output stage. Accordingly, the operation speed of the pass element is improved by charging and discharging the current of the gate node of the pass element. LDO regulators with feedback voltage sensing architecture operate over an input voltage range of 3.3V to 4.5V and have a load current of up to 200mA at an output voltage of 3V. According to the simulation result, when the load current is 200mA, it is 73mV under the undershoot condition and 61mV under the overshoot condition.

• Journal of Semiconductor Engineering
• /
• v.3 no.1
• /
• pp.154-160
• /
• 2022

In this paper, we design a DC-DC boost converter with RF noise immunity to supply a stable positive output voltage for OLED displays. For RF noise immunity, an input voltage variation reduction circuit (IVVRC) is adopted to ensure display quality by reducing the undershoot and overshoot of output voltage. The boost converter for a positive voltage Vpos operates in the SPWM-PWM dual mode and has a dead-time controller using a dead-time detector, resulting in increased power efficiency. A chip was fabricated using a 0.18 um BCDMOS process. Measurement results show that power efficiency is 30% ~ 76% for load current range from 1 mA to 100 mA. The boost converter with the IVVRC has an overshoot of 6 mV and undershoot of 4 mV compared to a boost converter without that circuit with 18 mV and 20 mV, respectively.

• Journal of IKEEE
• /
• v.26 no.1
• /
• pp.124-128
• /
• 2022

Conventional LDO regulator external capacitors can reduce transient response characteristics such as overshoot and undershoot. However, the capacitorless LDO regulator proposed in this study applied body technology to the pass transistor to improve the transient response and provide excellent current drive capability. The operating conditions of the proposed LDO regulator are set to an input voltage that varies from 3.3V to 4.5V, a maximum load current of 200mA, and an output voltage of 3V. As a result of the measurement, it was found that when the load current was 100 mA, the voltage was 95 mV in the undershoot state and 105 mV in the overshoot state.

• Journal of IKEEE
• /
• v.24 no.2
• /
• pp.598-603
• /
• 2020

In this paper present a Low Drop-Out(LDO) regulator that improves load transient characteristics due to the push-pull pass transistor structure is proposed. Improved load over the existing LDO regulator by improving the overshoot and undershoot entering the voltage line by adding the proposed push-pull circuit between the output stage of the error amplifier inside the LDO regulator and the gate stage of the pass transistor and the push-pull circuit at the output stage. It has a delta voltage value of transient characteristics. The proposed LDO structure was analyzed in Samsung 0.13um process using Cadence's Virtuoso, Spectre simulator.

• Journal of Power Electronics
• /
• v.9 no.3
• /
• pp.430-437
• /
• 2009

This paper presents the dynamic characteristics of buck and buck-boost dc-dc converters with digital filters. At first, the PID, the minimum phase FIR filter and the IIR filter controls are discussed in the buck dc-dc converter. Comparisons of the dynamic characteristics between the buck and buck-boost converters are then discussed. As a result, it is clarified that the superior dynamic characteristics are realized in the IIR filter method. In the buck converter, the undershoot is less than 2% and the transient time is less than 0.4ms. On the other hand, in the buck-boost converter, the undershoot is about 3%. However, the transient time is approximately over 4ms because the output capacitance is too large to suppress the output voltage ripple in this type of converter.

• Proceedings of the KIPE Conference
• /
• 2017.07a
• /
• pp.74-75
• /
• 2017

This paper proposes a control scheme of the voltage ripple suppression for the permanent magnet exciter generator. The output voltage of the permanent magnet excitation generator is affected by the field current, load current and the engine speed. The engine speed can be controlled by the governor. But, the actual frequency is changed at the starting and a sudden load variation. As a result, output voltage overshoot and undershoot can decrease the power quality in the grid system. The proposed control scheme uses a frequency factor to control the field current of the generator for the voltage ripple reduction. Because of the linkage flux is proportional to the frequency, the instantaneous frequency can consider the linkage flux. The proposed control method shows the improved control performance for the permanent magnet excitation generator through simulation.

• Journal of the Korean Society for Railway
• /
• v.18 no.6
• /
• pp.533-542
• /
• 2015

This paper suggest away to maintain constant power through trolley wire by transferring increased line voltage to the AC main line while changing the mode from Converter(Forward) to Inverter(Reverse) when the line voltage is increased due to regenerative power when the train stops, This paper suggests a Double Converter DC substation that can create regenerative power when the train stops reusable. We also proposed using a simulation tool, the optimal Thyrister firing angle that can minimize the undershoot and overshoot that occurs when transferring the mode from Converter to Inverter for quality improvement of DC voltage in the Double Converter in the DC substation from the Busan Urban Subway.

• ETRI Journal
• /
• v.37 no.5
• /
• pp.961-971
• /
• 2015

This paper proposes a 250 mV supply voltage digital low-dropout (LDO) regulator. The proposed LDO regulator reduces the supply voltage to 250 mV by implementing with all digital circuits in a$0.11{\mu}m$ CMOS process. The fast current tracking scheme achieves the fast settling time of the output voltage by eliminating the ringing problem. The over-voltage and under-voltage detection circuits decrease the overshoot and undershoot voltages by changing the switch array current rapidly. The switch bias circuit reduces the size of the current switch array to 1/3, which applies a forward body bias voltage at low supply voltage. The fabricated LDO regulator worked at 0.25 V to 1.2 V supply voltage. It achieved 250 mV supply voltage and 220 mV output voltage with 99.5% current efficiency and 8 mV ripple voltage at $20{\mu}A$ to $200{\mu}A$ load current.

• Transactions of the Korean hydrogen and new energy society
• /
• v.15 no.3
• /
• pp.175-186
• /
• 2004

In this paper, we developed the dynamic model of a fuel cell system suitable for controller design and system operation. The transient phenomena captured in the model include the flow characteristics and inertia dynamics of the compressor, the intake manifold filling dynamics, oxygen partial pressures and membrane humidity on the fuel cell voltage. In the simulations, we paid attention to the transient behavior of stack voltage and compressor pressure, stoichiometric ratio. Simulation results are presented to demonstrate the model capability. For load current following, stack voltage dynamic characteristics are plotted to understand the Electro-chemistry involved with the fuel cell system. Compressor pressure and stoichiometric ratio are strongly coupled, and independent parameters may interfere with each other, dynamic response, undershoot and overshoot.

• ETRI Journal
• /
• v.42 no.5
• /
• pp.790-798
• /
• 2020

Herein, a low-ripple coarse-fine digital low-dropout regulator (D-LDO) without ringing in the transient state is proposed. Conventional D-LDO suffers from a ringing problem when settling the output voltage at a large load transition, which increases the settling time. The proposed D-LDO removes the ringing and reduces the settling time using an auxiliary power stage which adjusts its output current to a load current in the transient state. It also achieves a low output ripple voltage using a comparator with a complete comparison signal. The proposed D-LDO was fabricated using a 65-nm CMOS process with an area of 0.0056 μ㎡. The undershoot and overshoot were 47 mV and 23 mV, respectively, when the load current was changed from 10 mA to 100 mA within an edge time of 20 ns. The settling time decreased from 2.1 ㎲ to 130 ns and the ripple voltage was 3 mV with a quiescent current of 75 ㎂.