• Proceedings of the Korean Information Science Society Conference
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• 2008.06a
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• pp.179-180
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• 2008

• ETRI Journal
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• v.43 no.5
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• pp.900-908
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• 2021

This paper proposes thermometer-code latches having five and six transistors for unidirectional and bidirectional thermometer-code shift-registers, respectively. The proposed latches omit the set and reset transistors by changing from two supply voltage nodes to the set and reset signals in the cross-coupled inverter. They set or reset the data by changing the supply voltage to ground in either of two inverters. They reduce the number of transistors to five and six compared with the conventional thermometer-code latches having six and eight transistors, respectively. The proposed thermometer-code latches were simulated using a 65 nm complementary metal-oxide-semiconductor (CMOS) process. For comparison, the proposed and conventional latches are adapted to the 64 bit thermometer-code shift-registers. The proposed unidirectional and bidirectional shift-registers occupy 140 ㎛² and 197 ㎛², respectively. Their consumption powers are 4.6 ㎼ and 5.3 ㎼ at a 100 MHz clock frequency with the supply voltage of 1.2 V. They decrease the areas by 16% and 13% compared with the conventional thermometer-code shift-register.

• Journal of IKEEE
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• v.8 no.2 s.15
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• pp.166-171
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• 2004

This paper describes a CMOS time to digital converter (TDC) that measures the interval between two signals and converts to a digital signal. There are various methods to measure the time interval. But several architectures have a limitation in resolution and in conversion time. Moreover, they have complex algorithms. But the proposed TDC circuit has achieved a high resolution (25ps) by using a high-speed digital sampler and simple algorithm. The sampler detects when input signals comes into the TDC and output is coded. The proposed multiphase clock generator was also implemented to achieve 25p resolution.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.3
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• pp.18-27
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• 1994

An 8-bit 2-stage pipelined current mode A/D converter is designed with a new architecture, where the wideband track-and-hold amplifiers which have 2 integrators in parallel sample input signal twice per clock cycle. The conversion speed of the A-D converter is two times faster than that of conventional pipelined method. The converter is designed to be operated at the power supply voltage of 3.3V with the input dynamic range of 0-256$\mu$A. HSPICE simulation results show the performance of up to 55Msamples/s and power consumption of 150mW with the parameters of ISRC $1.5\mu$m BICMOS process. The chip area is 3${\times}4mm^{2}$.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.10a
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• pp.106-109
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• 2004

In this project, we have developed the eye-safe LRF system of 1.54 ${\mu}{\textrm}{m}$ wavelength using OPO. The maximum measured distance was 3.7km in outdoor experiment. We used Nd：YAG (1064nm) as a laser medium. It was applied BBO to construct the system. We also developed a time-counter for the range finder using a method of TOF (time of flight). The counter-clock used at the time counter was 320MHz making resolution within $\pm$1m. Start and stop signals were detected by two channel systems using PIN and APD. The LRF's repetition rate was 4 times per minute. The energy was measured to be over 9mJ. And, pulse-duration was 23ns. Resolution was $\pm$2m at the distance measurement using a target.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.3C
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• pp.368-373
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• 2004

Extremely fine tine resolution of ultra-wideband (UWB) signal poses a new problems to the system designer. A reasonable accuracy of the system clock is necessary to process signals with such a high space resolution. A useful way of illustrating the time resolution of a signal is to evaluate the ambiguity function. The ambiguity function for carrierless UWB defined using the time mismatch and time scaling factor as its two parameters. The UWB ambiguity function is evaluated for various signaling schemes of impulse radio.

• Journal of Sensor Science and Technology
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• v.21 no.5
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• pp.389-393
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• 2012

A chaotic oscillator with light controllability was designed. The proposed chaotic oscillator consists of a photo sensor, two phase clock driven MOS switches, nonlinear function blocks for chaotic signal generation. SPICE circuit analysis using a 0.35 um CMOS process parameters was performed for its chaotic dynamics. And we confirmed that chaotic behaviors of the circuit can be controlled according to light intensity. By SPICE simulation, chaotic dynamics by time waveforms, frequency analysis was analyzed. SPICE results showed that proposed circuit can make various light-controlled chaotic signals.

• Journal of electromagnetic engineering and science
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• v.17 no.1
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• pp.39-43
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• 2017

In this paper, a systematic and statistical calibration technique was implemented to calibrate a high-speed signal converting system containing multiple digital-to-analog converters (DACs). The systematic error (especially the imbalance between DACs) in the current combining network of the multi-DAC system was modeled and corrected by calculating the path coefficients for individual DACs with wideband reference signals. Furthermore, by applying a Kalman filter to suppress noise from quantization and clock jitter, accurate coefficients with minimum noise were identified. For correcting an arbitrary waveform generator with two DACs, a co-simulation platform was implemented to estimate the system degradation and its corrected performance. Simulation results showed that after correction with 4.8 Gbps QAM signal, the signal-to-noise-ratio improved by approximately 4.5 dB and the error-vector-magnitude improved from 4.1% to 1.12% over 0.96 GHz bandwidth.

• 한국정보통신설비학회:학술대회논문집
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• 2005.08a
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• pp.154-158
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• 2005

In this paper, we design optical receiver composed of CDR(clock and data recovery), SA(sense amp), TIA(transimpe dence amplifier), and decision circuit. The optical receiver can be classified to two main block, one is Deserializer composed of CDR and SA, another is PD receiver composed of preamplifier(샴), peak detector, etc. In this paper, we propose CDR using delayed data topology that could improve defects of existing CDR. The optical receiver that is proposed in this paper has the role of translation a 1.25 Gb/s optical signal to $10{\times}125 Mb/s$ array electric signals. This optical receiver is verified by simulator(hspice) using 0.35 um CMOS technology.

• Proceedings of the KIEE Conference
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• 1996.07b
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• pp.970-973
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• 1996

In this paper, Modified GPS Kalman filter algorithms which allow user to estimate its position when the number of visible GPS satellites becomes less than four are presented. They are derived using the previous estimation of altitude and clock bias. Thus, it is possible to estimate 3-dimensional user position even when only two GPS satellites are visible. The algorithms are ideally suited to car navigation in urban areas where lack of GPS visibility is the major problem because of the frequent blockage of the GPS signals by tall buildings and other structures. Simulation results in this paper show that modified GPS Kalman filter provide better performances than a general GPS Kalman filter or any other instantaneous GPS solution algorithm, especially in the case which the number of visible GPS satellites becomes less than four.