• 전기학회논문지
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• 제60권4호
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• pp.880-884
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• 2011

The matrix-type superconducting fault current limiter (MSFCL) consists of the trigger and current-limiting parts. The trigger part with reactors connected in parallel improves the quenching characteristics by applying the external magnetic field into the superconducting units. The current-limiting part with superconducting units connected in parallel and shunt reactors connected in series limit the fault current when the fault occurs. We developed the integrated reactor with the trigger and the current-limiting parts to apply high external magnetic field into the superconducting units. This was composed of a superconducting unit for the trigger part and two superconducting units for the current-limiting parts. We confirmed that the external magnetic field generated in the MSFCL with an integrated reactor was larger than that of the MSFCL with the separated reactors. So the differences of voltages generated between superconducting units were decreased in the difference according to the increment of the applied voltage. The whole magnitude of the SFCL was reduced because the volume of an integrated reactor could be reduced by one-third than that of the separated reactors. We confirmed that the critical behavior between the superconducting units in the MSFCL with an integrated reactor was more improved than that of the MSFCL with the separated reactors.

• 전기전자학회논문지
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• 제19권2호
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• pp.265-270
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• 2015

본 논문에서는 높은 홀딩 전압을 갖는 SCR(silicon-controlled rectifier)기반 양 방향성 ESD 보호회로를 제안하였다. 일반적인 ESD 보호회로와 달리 양방향의 ESD Stress mode의 방전경로를 제공하며 높은 홀딩전압으로 latch-up면역 특성을 갖어 효과적인 ESD보호를 제공한다. 또한, 높은 홀딩전압을 위한 설계변수인 Gate Length와 N+bridge Length의 길이 변화에 따른 시뮬레이션을 Synopsys사의 TCAD 시뮬레이터를 사용하여 확인 하였다. 시뮬레이션 결과 2.1V에서 6.5V까지 홀딩 전압의 증가로 latch-up 면역 특성을 개선 하였으며, 기존 SCR보다 6.5V의 낮은 트리거 전압특성을 갖고 있어 제안된 ESD 보호 회로는 5V 이상의 공급전압을 갖는 application에 적용 가능하다.

• 전기전자학회논문지
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• 제10권2호통권19호
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• pp.149-155
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• 2006

In this study, the design of low voltage DC-DC converter with low triggering ESD (Electro-Static Discharge) protection circuit was investigated. The purpose of this paper is design optimization for low voltage(2.5V to 5.5V input range) DC-DC converter using CMOS switch. In CMOS switch environment, a dominant loss component is not switching loss but conduction loss at 1.2MHz switching frequency. In this study a constant frequency PWM converter with synchronous rectifier is used. And zener Triggered SCR device to protect the ESD phenomenon was designed. This structure reduces the trigger voltage by making the zener junction between the lateral PNP and base of lateral NPN in SCR structure. The triggering voltage was simulated to 8V.

• 전기전자학회논문지
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• 제11권1호통권20호
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• pp.54-60
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• 2007

본 연구에서는 고속 I/0 인터페이스용 ESD(Electro-Static Discharge)보호소자로서 SCR(Silicon Controlled Rectifier)구조에 기반한 새로운 구조의 ESD보호소자인 N/P-type Low Voltage Triggered Silicon-Controlled Rectifier(NPLVTSCR)을 제안하였다. 제안된 NPLVTSCR은 기존 SCR이 갖는 높은 트리거 전압($\sim$20V)을 낮추고 ($\sim$5V) 또한 정상상태에서의 보호소자의 래치업 현상을 줄일 수 있다. 본 연구에서 제안된 NPLVTSCR의 전기적 특성 및 ESB감내특성을 확인하기 위하여 TCAD툴을 이용하여 시뮬레이션을 수행하였으며, 또한 TSMC 90nm공정에서 테스트 패턴을 제작하여 측정을 수행하였다. 시뮬레이션 및 측정 결과를 통해, NPLVTSCR은 PMOS 게이트 길이에 따라 3.2V $\sim$ 7.5V의 트리거링 전압과 2.3V $\sim$ 3.2V의 홀딩전압을 갖으며, 약 2kV의 HBM ESD 감내특성을 갖는 것을 확인 할 수 있었다.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2018년도 추계학술대회
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• pp.35-38
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• 2018

본 논문에서는 DC 유형의 에너지 하베스팅을 위한 저전력 MPPT 인터페이스 회로를 설계하였다. 제안된 회로는 크게 MPPT controller, bias generator, voltage detector로 구성된다. MPPT controller는 schmitt trigger로 구성된 MPG(MPPT Pulse Generator)와 에너지 유형(빛, 열)에 따라 동작하는 logic gate와 sample/hold 회로로 구성된다. Bias generator는 beta multiplier 구조를 적용하여 설계되었으며, voltage detector는 bulk-driven comparator와 2단 buffer를 이용하여 설계되었다. 제안된 회로는 $0.35{\mu}m$ CMOS 공정으로 설계하였다. 모의실험 결과 설계된 회로는 3V 이내의 입력전압에서 100nA보다 작은 전류를 소모하며, 최대 전력효율은 99.7%이다. 설계된 회로의 칩 면적은 $1151{\mu}m{\times}940{\mu}m$이다.

• 전력전자학회논문지
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• 제23권4호
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• pp.281-285
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• 2018

An isolated feedback method for measuring the inverter DC-link voltage is proposed. This method provides a simple and economical solution to inverter control systems that use a flyback converter as a controller power supply. In the proposed method, data on the DC-link voltage are acquired when the primary side voltage appears on the secondary side of the flyback transformer, thereby eliminating the need to adopt an extra signal isolation method. To solve the non-synchronization problem between the flyback converter switching and main controller sampling, the external interrupt function of the micro-controller is used as a trigger signal for the A/D conversion.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 하계학술대회 논문집 F
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• pp.1869-1871
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• 1998

In this paper, we designed and fabricated a fast switching system for high power pulse. This system consists of a voltage conversion circuit, high voltage charging circuit, trigger circuit, and discharging circuit. Especially discharging line is designed by strip-line for low inductance and resistance. The experimental result is that current slew rate of the system is 6.67kA/86ns and this result is fully qualified for initiating EBW or EFI

• 전기전자학회논문지
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• 제10권2호통권19호
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• pp.141-148
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• 2006

In this study, the design of advanced LVDS(Low Voltage Differential Signaling) I/O interface circuit with new structural low triggering ESD (Electro-Static Discharge) protection circuit was investigated. Due to the differential transmission technique and low signal swing range, maximum transmission data ratio of designed LVDS transmitter was simulated to 5Gbps. And Zener Triggered SCR devices to protect the ESD Phenomenon were designed. This structure reduces the trigger voltage by making the zener junction between the lateral PNP and base of lateral NPN in SCR structure. The triggering voltage was simulated to 5.8V. Finally, The high speed I/O interface circuit with the low triggered ESD protection device in one-chip was designed.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 춘계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.215-217
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• 2001

This paper describes an all solid-state switch pulse generator for various applications where square pulse voltage is required. The pulse generator produces various voltage pulses: voltage $5{\sim}100kV$. current $10{\sim}200A$, pulse width $1{\sim}10{\mu}sec$, repetition rate up to 500Hz. The output power is the combination of these parameters up to 10kW. It consists of a DC-DC converter and several pulse generating modules which are connected in series to obtain higher pulse voltage. Each module contains semiconductor switches (IGBT's), energy storage capacitors and control units to trigger switches. The structure and operational principle are described and the protection circuit for reliable operation is suggested. Experimental results show that the pulse generator can be used for applications with nonlinear loads.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 E
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• pp.2189-2191
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• 1999

To improve the reliability of the klystron-modulator systems, the stable operations of the thyratron an important factor of the system are required. The thyratron always has a possibility of self-fire according to the conditions of the applied high voltage and this induces the system fault. Therefore a command charging method was introduced to reduce the applied tim8 of the high voltage into the thyratron. The high voltage switch used in the command charging method is the SCR (1.6 kV, 50A) and consists of 10 SCRs in series to discharge 10 kV. A pulse transformer was used to apply the trigger pulse. The objectives of this research are the fabrication of the semiconductor switch and the study of the experimental result of the operation characteristics of the high voltage semiconductor switch.