• The Transactions of the Korean Institute of Electrical Engineers P
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• v.58 no.1
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• pp.85-89
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• 2009

We investigated the quench characteristics in accordance with increase of turns number of trigger coil and shunt resistance of matrix-type superconducting fault current limiter (SFCL) with $2{\times}3$ array. The matrix-type SFCL consists of the trigger part to apply magnetic field and the current-limiting part to limit fault current. The fault current limiting characteristics according to the increase of magnetic field and applied voltage were nearly same. This is because the application of magnetic field hasn't an affect on total impedance of the SFCL. When turns number of a reactor increased, the voltage difference between two superconducting units in the current-limiting part according was decreased. The resistance difference generated in two superconducting units was also decreased. Therefore, we confirmed that the differences of the critical behaviors between superconducting units were reduced by application of magnetic field. By this results, we could decide the optimum turns number of reactor to apply magnetic field.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.625-631
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• 2014

We propose a compact power-on reset circuit consisting of a switched capacitor, a capacitor, and a Schmitt trigger inverter. A switched capacitor working with a clock signal charges the capacitor. Thus, the voltage across the capacitor is increased toward the supply voltage. The circuit provides a reset pulse until the voltage across the capacitor reaches the high threshold voltage of the Schmitt trigger inverter. The proposed circuit is simple, compact, has no static power consumption, and works for a wide range of power-on rising times. Furthermore, the clock signal is available while the reset pulse is activated. The proposed circuit works for up to 6 s of power-on rising time, and occupies a $60{\times}30{\mu}m^2$ active area.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.2
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• pp.150-154
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• 2019

In the design of semiconductor integrated circuits, ESD is one of the important issues related to product quality improvement and reliability. In particular, as the process progresses and the thickness of the gate oxide film decreases, ESD is recognized as an important problem of integrated circuit design. Many ESD protection circuits have been studied to solve such ESD problems. In addition, the proposed device can modify the existing SCR structure without adding external circuit to effectively protect the gate oxide of the internal circuit by low trigger voltage, and prevent the undesired latch-up phenomenon in the steady state with high holding voltage. In this paper, SCR-based novel ESD(Electro-Static Discharge) device with the high holding voltage has been proposed. The proposed device has the lower triggering voltage without an external trigger circuitry and the high holding voltage to prevent latch-up phenomenon during the normal condition. Using TCAD simulation results, not only the design factors that influence the holding voltage, but also comparison of conventional ESD protection device(ggNMOS, SCR), are explained. The proposed device was fabricated using 0.35um BCD process and was measured electrical characteristic and robustness. In the result, the proposed device has triggering voltage of 13.1V and holding voltage of 11.4V and HBM 5kV, MM 250V ESD robustness.

• Journal of IKEEE
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• v.25 no.2
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• pp.280-284
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• 2021

In this paper, a new ESD protection circuit is proposed to improve the snapback characteristics. The proposed a new structure ESD protection circuit applying the conventional SCR structural change and stack structure. The electrical characteristics of the structure using penta-well and double trigger were analyzed, and the trigger voltage and holding voltage were improved by applying the stack structure. The electron current and total current flow were analyzed through the TCAD simulation. The characteristics of the latch-up immunity and excellent snapback characteristics were confirmed. The electrical characteristics of the proposed ESD protection circuit were analyzed through HBM modeling after forming a structure through TCAD simulator.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.11
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• pp.1274-1281
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• 1988

A new voltage-controlled oscillator based on a voltage-controlled integrator has been developed. It consists of a Schmitt-trigger and a voltage-controlled integrator, which is realized by an operational transconductance amplifier (OTA) and a grounded capacitor. The input control voltage changes the time constant of the integrator, and hence the oscillation frequency. The SPICE simulation shows that a prototype circuit, which oscillates at 12.21 KHz at 0 V, has the conversion sencitivity 2,437 Hz/V and the residual nonlinearity less than 0.68% in a control voltage range from -2 V to 2 V. It also shows that the circuit provides a temperature drift less than + 250 ppm/$^{\circ}$C for frequencies up to 100 KHz.

• Journal of IKEEE
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• v.21 no.2
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• pp.150-153
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• 2017

In this paper, a structure of GCNMOS based ESD protection circuit using floating-body technique is proposed. TCAD simulation of Synopsys was used to compare with the conventional GGNMOS and GCNMOS. Compared with the conventional GCNMOS, the proposed ESD protection circuit has lower trigger voltage and faster turn-on-time than conventional circuit because of the added NMOSFET. In the simulation result, the triggering voltage of the proposed ESD protection circuit is 4.86V and the turn-on-time is 1.47ns.

• Proceedings of the KIEE Conference
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• 1989.11a
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• pp.142-144
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• 1989

Triggering characteristics of a trigatron spark gap have been studied by measuring self-emission UV light. By combining the measurement of the UV light with that of the trigger gap voltage and the lain discharge current, we distinguished clearly the differences between the trigatron operations in which the lain discharge occurs after the trigger discharge in the case of sale polarity between the trigger pin and the lain electrode at the opposite side, and the lain gap breakdown takes place before the formation of the trigger spark in the case of different polarity. We show the observation of UV radiation with the other electromagnetic measurements is a simple and reliable scheme to investigate the triggering properties of the trigatron spark gaps.

• ETRI Journal
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• v.39 no.5
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• pp.746-755
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• 2017

In this paper, an electrostatic discharge (ESD) protection circuit is designed for use as a 12 V power clamp by using a parasitic-diode-triggered silicon controlled rectifier. The breakdown voltage and trigger voltage ($V_t$) of the proposed ESD protection circuit are improved by varying the length between the n-well and the p-well, and by adding $n^+/p^+$ floating regions. Moreover, the holding voltage ($V_h$) is improved by using segmented technology. The proposed circuit was fabricated using a $0.18-{\mu}m$ bipolar-CMOS-DMOS process with a width of $100{\mu}m$. The electrical characteristics and robustness of the proposed ESD circuit were analyzed using transmission line pulse measurements and an ESD pulse generator. The electrical characteristics of the proposed circuit were also analyzed at high temperature (300 K to 500 K) to verify thermal performance. After optimization, the $V_t$ of the proposed circuit increased from 14 V to 27.8 V, and $V_h$ increased from 5.3 V to 13.6 V. The proposed circuit exhibited good robustness characteristics, enduring human-body-model surges at 7.4 kV and machine-model surges at 450 V.

• Journal of IKEEE
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• v.23 no.4
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• pp.1309-1313
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• 2019

In this paper, the electrical characteristics of Gate grounded NMOS(GGNMOS), Lateral insulated gate bipolar transistor(LIGBT), Silicon Controlled Rectifier(SCR), and Proposed ESD protection device were compared and analyzed. First, the trigger voltage and holding voltage were verified by simulating the I-V characteristic curve for each device. After that, the robustness was confirmed by HBM 4k simulation for each device. As a result of HBM 4k simulation, the maximum temperature of the proposed ESD protection device is lower than that of GGNMOS and GGLIGBT and SCR, which means that the robustness is improved, which means that the ESD protection device is excellent in terms of reliability.

• Journal of IKEEE
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• v.22 no.3
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• pp.836-841
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• 2018

In this paper, This paper is based on the conventional ESD protection circuits SCR and LVTSCR. Also, the SCR-based ESD protection circuit, which is different from the conventional structure, is presented and tested for variations in the trigger voltage and holding voltage. Due to the insertion of additional N +, P + regions, the newly added SCR-based protection circuit have improved electrical characteristics. To discuss the electrical characteristics of the proposed circuit, Synopsys T-CAD simulation data was shown.