• Proceedings of the Korean Powder Metallurgy Institute Conference
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• 2006.09b
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• pp.1048-1049
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• 2006

Rapidly solidified ribbon-consolidation processing was applied for preparation of high strength bulk Mg-Zn-Gd alloys. Mg alloys have been used in automotive and aerospace industries. Rapid solidification (RS) process is suitable for the development of high strength Mg alloys, because the process realizes grain-refinement, increase in homogeneity, and so on. Recently, several nanocrystalline Mg-Zn-Y alloys with high specific tensile strength and large elongation have been developed by rapidly solidified powder metallurgy (RS P/M) process. Mg-Zn-Y RS P/M alloys are characterized by long period ordered (LPO) structure and sub-micron fine grains. The both additions of rare earth elements and zinc remarkably improved the mechanical properties of RS Mg alloys. Mg-Zn-Gd alloy also forms LPO structure in -Mg matrix coherently, therefore, it is expected that the RS Mg-Zn-Gd alloys have excellent mechanical properties. In this study, we have developed high strength RS Mg-Zn-Gd alloys with LPO structure and nanometer-scale precipitates by RS ribbon-consolidation processing. $Mg_{97}Zn_1Gd_2$ and $Mg_{95.5}Zn_{1.5}Gd_3$ and $Mg_{94}Zn_2Gd_4$ bulk alloys exhibited high tensile yield strength (470 MPa and 525 MPa and 566 MPa) and large elongation (5.5% and 2.8% and 2.4%).

• Journal of the Korea Society for Simulation
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• v.9 no.4
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• pp.51-58
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• 2000

The control of the data retention time is a main issue for realizing future high density dynamic random access memory. The novel junction process scheme in sub-micron DRAM cell with STI(Shallow Trench Isolation) has been investigated to improve the tail component in the retention time distribution which is of great importance in DRAM characteristics. In this' paper, we propose the new implantation scheme by gate-related ion beam shadowing effect and buffer-enhanced ${\Delta}Rp$ (projected standard deviation) increase using buffered N-implantation with tilt and 4X(4 times)-rotation that is designed on the basis of the local-field-enhancement model of the tail component. We report an excellent tail improvement of the retention time distribution attributed to the reduction of electric field across the cell junction due to the redistribution of N-concentration which is Intentionally caused by ion Beam Shadowing and Buffering Effect using tilt implantation with 4X-rotation. And also, we suggest the least requirements for adoption of this new implantation scheme and the method to optimize the key parameters such as tilt angle, rotation number, Rp compensation and Nd/Na ratio. We used MEDICI Simulator to confirm the junction device characteristics. And measured the refresh time using the ADVAN Probe tester.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.7
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• pp.510-514
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• 2018

This study discusses and demonstrates the structural stability of highly ordered Pt patterns formed on a transparent and flexible substrate through the process of nanotransfer printing (nTP). Bending tests comprising approximately 1,000 cycles were conducted for observing Pt line patterns with a width of $1{\mu}m$ formed along the direction of the horizontal (x-axis) and vertical (y-axis) axes ($15mm{\times}15mm$); and adhesion tests were performed with an ultrasonicator for a period greater than ten minutes, to analyze the Pt crossbar patterns. The durability of both types of patterns was systematically analyzed by employing various microscopes. The results show that the Pt line and Pt crossbar patterns obtained through nTP are structurally stable and do not exhibit any cracks, breaks, or damages. These results corroborate that nTP is a promising nanotechnology that can be applied to flexible electronic devices. Furthermore, the multiple patterns obtained through nTP can improve the working performance of flexible devices by providing excellent structural stability.

• The KIPS Transactions:PartA
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• v.16A no.1
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• pp.27-34
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• 2009

Recently, power saving with high performance is one of the hot issues in the mobile systems. Various technologies are introduced to achieve low-power processors, which include sub-micron semiconductor fabrication, voltage scaling, speed scaling and etc. In this paper, we introduce a new method that reduces of energy loss at the data cache. Our methods take the benefits in terms of speed and energy loss using selective way precharging of way prediction with concurrent way selecting. By the simulation results, our method achieves 10.2% energy saving compared to the way prediction method, and 56.4% energy saving compared to the common data cache structure.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.12
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• pp.1056-1061
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• 2007

A sublimation epitaxial method, referred to as the Closed Space Technique (CST) was adopted to produce thick SiC epitaxial layers for power device applications. In this study, we aimed to systematically investigate surface morphologies and electrical properties of SiC epitaxial layers grown with varying a SiC/Al ratio in a SiC source powder during the sublimation growth using the CST method. The surface morphology was dramatically changed with varying the SiC/Al ratio. When the SiC/Al ratio of 90/1 was used, the step bunching was not observed in this magnification and the ratio of SiC/Al is an optimized range to grow of p-type SiC epitaxial layer. It was confirmed that the acceptor concentration of epitaxial layer was continuously decreased with increasing the SiC/Al ratio. 4H-SiC MESFETs haying a micron-gate length were fabricated using a lithography process and their current-voltage performances were characterized. It was confirmed that the increase of the negative voltage applied on the gate reduced the drain current, showing normal operation of FET device.

• Bulletin of the Korean Chemical Society
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• v.33 no.4
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• pp.1128-1134
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• 2012

We investigated a new method for patterning organic field-effect transistors (OFETs) using a photopatternable conducting polymer nanocomposite, consisting of poly(3-hexylthiophene) (P3HT)-coated gold nanoparticles (AuNPs) that had been modified with a photoreactive cinnamate group, to form P3HT-AuNP-CI. We found that the addition of the cinnamate group to the nanoparticle surface assisted the preparation of a solvent-resistive semiconducting film and preserved the P3HT ordering, which was interrupted by Au-P3HT interactions, as well as provided UV-controllable electrical properties. The P3HT-AuNPs-CI films could be microscale-patterned via a UV crosslinking photoreaction, represented as a promising photopatternable semiconductor material for use in advanced applications, with tunable electrical properties for fabrication of sub-micron and microscale electronic devices.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.11a
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• pp.185-188
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• 2001

Chemical mechanical polishing(CMP) process is widely used for global planarization of inter-metal dielectric (IMD) layer and inter-layer dielectric (ILD) for deep sub-micron technology. However, as the IMD and ILD layer gets thinner, defects such as micro-scratch lead to severe circuit failure, which affect yield. In this paper, for the improvement of CMP Process, deionized water (DIW) pressure, purified $N_2$ (P$N_2$) gas, slurry filter and high spray bar were installed. Our experimental results show that DIW pressure and P$N_2$ gas factors were not related with removal rate, but edge hot-spot of patterned wafer had a serious relation. Also, the filter installation in CMP polisher could reduce defects after CMP process, it is shown that slurry filter plays an important role in determining consumable pad lifetime. The filter lifetime is dominated by the defects. However, the slurry filter is impossible to prevent defect-causing particles perfectly. Thus, we suggest that it is necessary to install the high spray bar of de-ionized water (DIW) with high pressure, to overcome the weak-point of slurry filter. Finally, we could expect the improvements of throughput, yield and stability in the ULSI fabrication process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.05c
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• pp.41-44
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• 2003

As the device feature size is reduced to the deep sub-micron regime, the chemical mechanical polishing (CMP) technology is widely recognized as the most promising method to achieve the global planarization of the multilevel interconnection for ULSI applications. However, cost of ownership (COO) and cost of consumables (COC) were relatively increased because of expensive slurry. In this paper, the effects of different slurry composition on the oxide CMP characteristics were investigated to obtain the higher removal rate and lower non-uniformity. We prepared the various kinds of slurry. In order to save the costs of slurry, the original slurry was diluted by de-ionized water (DIW). And then, alunima abrasives were added in the diluted slurry in order to promote the mechanical force of diluted slurry.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.195-196
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• 2005

In recent years, as the needs of MOS's a high quality is desired to get the superior electrical characteristics and reliability on MOSFET. As an alternative gate dielectric have drawn considerable alternation due to their superior performance and reliability properties over MOSFET, 2'nd silicidation formation process has been proposed as a dielectric growth/annealing process. In this study the author observed process characteristics on MOS structure. In view points of the process characteristics of MOS capacitor, the oxygen & polysilicon was analyzed by SIMS analysis on l'st & 2'nd Ti process, the oxygen and Si2 contents[Count/sec] of 1.5e3 & 3.75e4 on l'st process and l.1e3 & 2.94e4 on 2'nd process, the Ti contents' of 8.2e18 & 6.5e18 on 1'st and 2'nd process. The sheet resistance[$\Omega/sq.$] was 4.5 & 4.0, the film stress[dyne/cm 2] of 1.09e10 & 1.075e10 on l'st and 2'nd process. I could achieved the superior MOS characteristics by 2'nd silicidation process.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.26 no.4
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• pp.637-643
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• 2002

The objective of this study is to provide a simple methodology to find optimum processing conditions to fabricate sub-micron structured DVD-RAM substrates with superb optical and geometrical properties. It was fecund that the birefringence, which is regarded as one of the most important optical properties for an optical disk, was very sensitive to the mold wall temperature history. Also, the integrity of the replication, represented by the land-groove structure and the radial tilt were influenced by the mold temperature and the compression pressure. A set of optimum conditions were obtained by applying Design of Experiment and the objective functions composed of three different objectives.