• Environmental Engineering Research
• /
• v.24 no.3
• /
• pp.382-388
• /
• 2019

Although nanobubbles attract significant attention, their characteristics and applications have not been thoroughly defined. There are diverse opinions about the definition of nanobubbles and controversy regarding methods that verify their characteristics. This study defines nanobubbles as having a size less than $1{\mu}m$. The generation of these sub-micron (nano) bubbles may be verified by induced coalescence or light scattering. The size of a sub-micron (nano) bubbles may be measured by optical, and confocal laser scanning microscopy. Also, the size may be estimated by the relationship of bubble size with the dissolved oxygen concentration. However, further research is required to accurately define the average bubble size. The zeta potential of sub-micron (nano) bubbles decreases as pH increases, and this trend is consistent for micron bubbles. When the bubble size is reduced to about 700-900 nm, they become stationary in water and lose buoyancy. This characteristic means that measuring the concentration of sub-micron (nano) bubbles by volume may be possible by irradiating them with ultrasonic waves, causing them to merge into micron bubbles. As mass transfer is a function of surface area and rising velocity, this strongly indicates that the application of sub-micron (nano) bubbles may significantly increase mass transfer rates in advanced oxidation and aeration processes.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1995.11a
• /
• pp.232-235
• /
• 1995

To improve the DIBL characteristics of deep sub micron BC PMOSFETs, the methods of DCI(Deep Channel Implantation) and Hale Implantation have been reported. In this study, using the process simulator TSUPREM4, we simulated the 0.25$\mu\textrm{m}$ and 0.45$\mu\textrm{m}$ gate length BC PMOSFETs applying the both methods to improve the DIBL characteristics, and their electric characteristics were compared to find the mothod suitable far deep sub-half micron BC PMOSFETs, using the device simulator MEDICI. So we found out that the method of Halo Implantation could be applied to deep sub-half micron BC PMOSFETs for 255 Mbit DRAM.

• Progress in Superconductivity and Cryogenics
• /
• v.23 no.3
• /
• pp.45-50
• /
• 2021

In this study, the effect of the size of B powder on the critical current density (J_c) of MgB₂ prepared by an in situ reaction process was investigated. Various combinations of B powders were made using a micron B, ball-milled B and nano B powders. Micron B powder was reduced by ball milling and the milled B powder was mixed with the micron B or nano B powder. The mixing ratios of the milled B and micron or nano B were 100:0, 50:50 and 0:100. Non-milled micron B powder was also mixed with nano powder in the same ratios. Pellets of (2B+Mg) prepared with various B mixing ratios were heat-treated to form MgB₂. T_c of MgB₂ decreased slightly when the milled B was used, whereas the J_c of MgB₂ increased with increasing amount of the milled B or the nano powder. The used of the milled B and nano B power promoted the formation MgB₂ during heat treatment. In addition to the enhanced formation of MgB₂, the use of the powders reduced the grain size of MgB₂. The use of the milled and nano B powder increased the J_c of MgB₂. The highest J_c was achieved when 100% nano B powder was used. The J_c enhancement is attributed to the high volume fraction of the superconducting phase (MgB₂) and the large grain boundaries, which induces the flux pinning at the magnetic fields.

• Proceedings of the Materials Research Society of Korea Conference
• /
• 2009.05a
• /
• pp.50.2-50.2
• /
• 2009

사파이어는 질화물계 광전자소자 제작 시 박막 성장 기판으로 주로 사용되어 최근 그 중요성이 부각되고 있다. 특히 미세 패턴이 형성된 사파이어 기판을 이용하여 질화물계 발광다이오드 소자를 제작하면 빛의 난반사가 증가하여 광추출효율에 큰 개선이 나타난다. 또한 사파이어는 화학적 안정성이 뛰어나고, 높은 강도를 지녀 나노임프린트 등 여러 가지 패터닝 공정에서 패턴 형성 몰드로도 응용될 수 있다. 그러나 이와 같은 사파이어의 화학적 안정성으로 인하여 sub-micron 크기의 미세 패턴을 형성하기 힘들며, 현재 사파이어의 패턴은 micron 크기로 제한되어 사용되고 있다. 본 연구에서는 나노임프린트 리소그라피(NIL)를 사용하여 사파이어 웨이퍼의 c-plane위에 sub-micron 크기의 hole 패턴 및 pillar 패턴을 형성하였다. 우선 Hole 패턴을 형성하기 위해 사파이어 기판 위에 금속 hard mask 패턴을 UV 임프린트 공정과 etch 공정을 통해 형성하였다. 그리고 이 금속 패턴을 mask로 사파이어를 ICP 식각을 하여 hole 패턴을 형성하였다. 또한 Pillar 패턴을 형성하기 위해 lift-off 공정을 이용하여 금속 마스크 패턴을 형성하였고 이를 ICP 식각을 통해 사파이어 기판 위에 pillar 패턴을 형성하였다.

• Proceedings of the Materials Research Society of Korea Conference
• /
• 1994.11a
• /
• pp.186-187
• /
• 1994

• Proceedings of the Materials Research Society of Korea Conference
• /
• 1996.05a
• /
• pp.64-64
• /
• 1996

• Proceedings of the Materials Research Society of Korea Conference
• /
• 1994.05a
• /
• pp.167-167
• /
• 1994

• Proceedings of the Materials Research Society of Korea Conference
• /
• 1993.05a
• /
• pp.91-92
• /
• 1993

• Proceedings of the Korean Magnestics Society Conference
• /
• 2005.06a
• /
• pp.104-105
• /
• 2005

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.33A no.10
• /
• pp.130-138
• /
• 1996

The size of a device needs to scale down to increase its integrity and speed. As the size of the device is reduced, the hot-carrier degradation that severely effects on device reliabilty is concerned. In this paper, sub-micron buried-channel P-MOSFETs were fabircated, and the hot-carrier effects were invetigated. Also the hot-carrier effect in the buired-channel P-MOSFETs and the surface-channel P-MOSFETs were compared with simulation programs using SUPREM-4 and MINIMOS-4. This paper showed that the electric characteristics of sub-micron P-MOSFET are different from those of N-MOSFET. Also it showed that the punchthrough voltage ( $V_{pt}$ ) was abruptly drop after applying the stress and became almost 0V when the channel lengths were shorter than 0.6.mu.m. The lower punchthrough voltage causes the device to operte poorly by the deterioration of cut-off characteries in the switching mode. We can conclude that the buried channel P-MOSFET for CMOS circuits has a limit of the channel length to be around 0.6.mu.m.