• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2000.04b
• /
• pp.180-183
• /
• 2000

Beginning with a brief introduction on near 100 nm or below CMOS devices, this paper addresses novel devices for future sub-100 nm CMOS. First, key issues such as gate materials, gate dielectric, source/drain, and channel in Si bulk CMOS devices are considered. CMOS devices with different channel doping and structure are introduced by explaining a figure of merit. Finally, novel device structures such as SOI, SiGe, and double-gate devices will be discussed for possible candidates for sub-100 nm CMOS.

• Proceedings of the IEEK Conference
• /
• 2002.06b
• /
• pp.237-240
• /
• 2002

In this W, a NiSi technology suitable for sub-100nm CMOS sevice is proposed. It seems that capping layer has little effect on the sheet resistance and junction leakage current when there is no thermal treatment. However, there happened agglomeration and drastic increase of Junction leakage current without capping layer. In other word, capping layer especially TiN capping layer is highly effective in suppressing thermal effect. It is shown that the sheet resistance of 0.12${\mu}{\textrm}{m}$ linewidth and shallow p+/n junction with NiSi were stable up to 700 t /30 minute thermal treatment.

• Proceedings of the IEEK Conference
• /
• 2004.06b
• /
• pp.343-346
• /
• 2004

This paper proposes a leakage-suppressed SRAM with dynamic power saying scheme for the future leakage-dominant sub-70-nm technology. By dynamically controlling the common source-line voltage ($V_{SL}$) of sleep cells, the sub-threshold leakage through these sleep cells can be reduced to be 1/10-1/100 due to the reverse body-bias effect, dram-induced barrier lowering (DIBL) and negative $V_{GS}$ effects. Moreover, the bit-ling leakage which mar introduce a fault during the read operation can be completely eliminated in this new SRAM. The dynamic $V_{SL}$ control can also reduce the bit-line swing during the write so that the dynamic power in write can be reduced. This new SRAM was fabricated in 0.35-${\mu}m$ CMOS process and more than $30\%$ of dynamic power saying is experimentally verified in the measurement. The leakage suppression scheme is expected to be able to reduce more than $90\%$ of total SRAM power in the future leakage-dominant 70-nm process.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.25 no.8
• /
• pp.1095-1102
• /
• 2021

A scalable ECC architecture with high scalability and flexibility between performance and hardware complexity is proposed. For architectural scalability, a modular arithmetic unit based on a one-dimensional array of processing element (PE) that performs finite field operations on 32-bit words in parallel was implemented, and the number of PEs used can be determined in the range of 1 to 8 for circuit synthesis. A scalable algorithms for word-based Montgomery multiplication and Montgomery inversion were adopted. As a result of implementing scalable ECC processor (sECCP) using 180-nm CMOS technology, it was implemented with 100 kGEs and 8.8 kbits of RAM when N_PE=1, and with 203 kGEs and 12.8 kbits of RAM when N_PE=8. The performance of sECCP with N_PE=1 and N_PE=8 was analyzed to be 110 PSMs/sec and 610 PSMs/sec, respectively, on P256R elliptic curve when operating at 100 MHz clock.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.40 no.12
• /
• pp.1-9
• /
• 2003

In this paper, a novel Ni silicide technology with Cobalt interlayer and Titanium Nitride(TiN) capping layer for sub 100 nm CMOS technologies is presented, and the device parameters are characterized. The thermal stability of hi silicide is improved a lot by applying co-interlayer at Ni/Si interface. TiN capping layer is also applied to prevent the abnormal oxidation of NiSi and to provide a smooth silicidc interface. The proposed NiSi structure showed almost same electrical properties such as little variation of sheet resistance, leakage current and drive current even after the post silicidation furnace annealing at $700^{\circ}C$ for 30 min. Therefore, it is confirmed that high thermal robust Ni silicide for the nano CMOS device is achieved by newly proposed Co/Ni/TiN structure.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.8 no.4
• /
• pp.289-294
• /
• 2008

A 77 GHz 3-stage low noise amplifier (LNA) employing one common source and two cascode stages is developed using $0.13{\mu}m$ CMOS process. To compensate for the low gain which is caused by lossy silicon substrate and parasitic element of CMOS transistor, positive feedback technique using parasitic inductance of bypass capacitor is adopted to cascode stages. The developed LNA shows gain of 7.2 dB, Sl1 of -16.5 dB and S22 of -19.8 dB at 77 GHz. The return loss bandwidth of LNA is 71.6 to 80.9 GHz (12%). The die size is as small as $0.7mm\times0.8mm$ by using bias line as inter-stage matching networks. This LNA shows possibility of 77 GHz automotive RADAR system using $0.13{\mu}m$ CMOS process, which has advantage in cost compared to sub-100 nm CMOS process.

• Journal of IKEEE
• /
• v.25 no.4
• /
• pp.625-633
• /
• 2021

This paper describes a scalable architecture for flexible hardware implementation of Montgomery modular multiplication. Our scalable modular multiplier architecture, which is based on a one-dimensional array of processing elements (PEs), performs word parallel operation and allows us to adjust computational performance and hardware complexity depending on the number of PEs used, N_PE. Based on the proposed architecture, we designed a scalable Montgomery modular multiplier (sMM) core supporting eight field sizes defined in SEC2. Synthesized with 180-nm CMOS cell library, our sMM core was implemented with 38,317 gate equivalents (GEs) and 139,390 GEs for N_PE=1 and N_PE=8, respectively. When operating with a 100 MHz clock, it was evaluated that 256-bit modular multiplications of 0.57 million times/sec for N_PE=1 and 3.5 million times/sec for N_PE=8 can be computed. Our sMM core has the advantage of enabling an optimized implementation by determining the number of PEs to be used in consideration of computational performance and hardware resources required in application fields, and it can be used as an IP (intellectual property) in scalable hardware design of elliptic curve cryptography (ECC).

• Korean Journal of Materials Research
• /
• v.17 no.2
• /
• pp.73-80
• /
• 2007

For the sub-65 nm CMOS process, it is necessary to develop a new silicide material and an accompanying process that allows the silicide to maintain a low sheet resistance and to have an enhanced thermal stability, thus providing for a wider process window. In this study, we have evaluated the property and unit process compatibility of newly proposed composite silicides. We fabricated composite silicide layers on single crystal silicon from $10nm-Ni_{1-x}Co_x/single-crystalline-Si(100),\;10nm-Ni_{1-x}Co_x/poly-crystalline-\;Si(100)$ wafers (x=0.2, 0.5, and 0.8) with the purpose of mimicking the silicides on source and drain actives and gates. Both the film structures were prepared by thermal evaporation and silicidized by rapid thermal annealing (RTA) from $700^{\circ}C\;to\;1100^{\circ}C$ for 40 seconds. The sheet resistance, cross-sectional microstructure, surface composition, were investigated using a four-point probe, a field emission scanning probe microscope, a field ion beam, an X-ray diffractometer, and an Auger electron depth profi1ing spectroscopy, respectively. Finally, our newly proposed composite silicides had a stable resistance up to $1100^{\circ}C$ and maintained it below $20{\Omega}/Sg$., while the conventional NiSi was limited to $700^{\circ}C$. All our results imply that the composite silicide made from NiCo alloy films may be a possible candidate for 65 nm-CMOS devices.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.13 no.5
• /
• pp.359-369
• /
• 2020

In this paper, we proposed a charge pump (CP) circuit that has a wide operating range while reducing the current mismatch for the PLL that generates the main clock of the CMOS X-Ray detector. The operating range and current mismatch of the CP circuit are determined by the characteristics of the current source circuit for the CP circuit. The proposed CP circuit is implemented with a wide operating current mirror bias circuit to secure a wide operating range and a cascode structure with a large output resistance to reduce current mismatch. The proposed wide operating range cascode CP circuit was fabricated as a chip using a 350nm CMOS process, and current matching characteristics were measured using a source measurement unit. At this time, the power supply voltage was 3.3 V and the CP circuit current ICP = 100 ㎂. The operating range of the proposed CP circuit is △VO_Swing=2.7V, and the maximum current mismatch is 5.15 % and the maximum current deviation is 2.64 %. The proposed CP circuit has low current mismatch characteristics and can cope with a wide frequency range, so it can be applied to systems requiring various clock speed.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2012.02a
• /
• pp.162-162
• /
• 2012

Sub 100 nm의 Complementary Metal-Oxide-Semiconductor (CMOS) 소자를 구동하기 위해서는 2.0 nm 이하의 $SiO_2$ oxide에 해당하는 전기적 특성이 요구된다. 그러나 2.0 nm 이하의 $SiO_2$에서는 누설 전류가 너무 크기 때문에 이를 대체하기 위해서 유전 상수 (dielectric permittivity)가 높은 $HfO_2$ (${\varepsilon}=25$), $Al_2O_3$, $HfO_2/Al_2O_3$ laminate 등의 high-k dielectric 물질들이 연구되고 있다[1]. High-k dielectric 물질의 전기적 특성은 박막 조성, 두께 및 전극과의 계면에 생성되는 계면 층이나 불순물(Impurity) 거동에 크게 의존하므로 High-k dielectric/전극(Metal or Si) 구조에서 조성 및 불순물의 거동에 대한 정확한 평가가 주요 쟁점으로 부각되고 있다. 이를 평가하기 위해 일반적으로 $Ar^+$ ion에 의한 depth profiling 분석이 진행되나 Oxygen 원자의 선택적 식각에 기인된 분석 깊이 분해능(Depth Resolution) 왜곡으로 계면 층의 형성이나 불순물의 거동을 정확하게 평가할 수 없다. 이러한 예로는 $Ta_2O_5$ 및 $SrBi_2Ta_2O_9$와 같은 다 성분 계 산화막에 $Ar^+$ ion 주사 시 발생하는 선택적인 식각(Preferential Sputtering) 때문에 박막의 실제 조성 및 거동을 평가하는 것은 어렵다고 보고된 바 있다[2,3]. 본 연구에서는 $90{\AA}$인 적층 $Hf_xO_y/Al_xO_y/Hf_xO_y$ 구조에서의 불순물 거동 분석 능력 확보 상 주요 인자인 깊이 분해능 개선을 Secondary Ion Mass Spectroscopy(SIMS)의 primary ion 종, impact energy 및 주사 각도를 변화시켜 ~1 nm 수준까지 구현하였다. 이러한 분석 깊이 분해능의 개선은 Low Impact Energy, 입사 이온의 glancing angle 및 Cluster ion 적용에 의존하며 이들 요인의 효과에 대해 비교/고찰하고자 한다.