Leakage-Suppressed SRAM with Dynamic Power Saving Scheme for Future Sub-70-nm CMOS Technology

70-nm 이하 급 초미세 CMOS 공정에서의 누설 전류 및 동적 전류 소비 억제 내장형 SRAM 설계

This paper proposes a leakage-suppressed SRAM with dynamic power saying scheme for the future leakage-dominant sub-70-nm technology. By dynamically controlling the common source-line voltage ($V_{SL}$) of sleep cells, the sub-threshold leakage through these sleep cells can be reduced to be 1/10-1/100 due to the reverse body-bias effect, dram-induced barrier lowering (DIBL) and negative $V_{GS}$ effects. Moreover, the bit-ling leakage which mar introduce a fault during the read operation can be completely eliminated in this new SRAM. The dynamic $V_{SL}$ control can also reduce the bit-line swing during the write so that the dynamic power in write can be reduced. This new SRAM was fabricated in 0.35-${\mu}m$ CMOS process and more than $30\%$ of dynamic power saying is experimentally verified in the measurement. The leakage suppression scheme is expected to be able to reduce more than $90\%$ of total SRAM power in the future leakage-dominant 70-nm process.