• Title/Summary/Keyword: source/drain

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A Study on Reaction Stability Between Nickel and Side-wall Materials With Silicidation Temperature (니켈실리사이드 제조온도에 따른 측벽물질과의 반응안정성 연구)

  • An, Yeong-Suk;Song, Oh-Sung
    • Korean Journal of Materials Research
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    • v.11 no.2
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    • pp.71-75
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    • 2001
  • The reaction stability of nickel with side-wall materials of SiO$_2$ and Si$_3$N$_4$ on p-type 4"(100) Si substrate were investigated. Ni on 1300 $\AA$ thick SiO$_2$ and 500 $\AA$ - thick Si$_3$N$_4$ were deposited. Then the samples were annealed at 400, 500, 750 and 100$0^{\circ}C$ for 30min, and the residual Ni layer was removed by a wet process. The interface reaction stability was probed by AES depth Profiling. No reaction was observed at the Ni/SiO$_2$ and Ni/Si$_3$N$_4$, interfaces at 400 and 50$0^{\circ}C$. At 75$0^{\circ}C$, no reaction occurred at Ni/SiO$_2$ interface, while $NiO_x$ and Si$_3$N$_4$ interdiffused at Ni/Si$_3$N$_4$ interface. At 100$0^{\circ}C$, Ni layers on SiO$_2$ and Si$_3$N$_4$ oxidized into $NiO_x$ and then $NiO_x$ interacted with side-wall materials. Once $NiO_x$ was formed, it was not removed in wet etching process and easily diffused into sidewall materials, which could lead to bridge effect of gate-source/drain.

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Gate length scaling behavior and improved frequency characteristics of In0.8Ga0.2As high-electron-mobility transistor, a core device for sensor and communication applications (센서 및 통신 응용 핵심 소재 In0.8Ga0.2As HEMT 소자의 게이트 길이 스케일링 및 주파수 특성 개선 연구)

  • Jo, Hyeon-Bhin;Kim, Dae-Hyun
    • Journal of Sensor Science and Technology
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    • v.30 no.6
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    • pp.436-440
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    • 2021
  • The impact of the gate length (Lg) on the DC and high-frequency characteristics of indium-rich In0.8Ga0.2As channel high-electron mobility transistors (HEMTs) on a 3-inch InP substrate was inverstigated. HEMTs with a source-to-drain spacing (LSD) of 0.8 ㎛ with different values of Lg ranging from 1 ㎛ to 19 nm were fabricated, and their DC and RF responses were measured and analyzed in detail. In addition, a T-shaped gate with a gate stem height as high as 200 nm was utilized to minimize the parasitic gate capacitance during device fabrication. The threshold voltage (VT) roll-off behavior against Lg was observed clearly, and the maximum transconductance (gm_max) improved as Lg scaled down to 19 nm. In particular, the device with an Lg of 19 nm with an LSD of 0.8 mm exhibited an excellent combination of DC and RF characteristics, such as a gm_max of 2.5 mS/㎛, On resistance (RON) of 261 Ω·㎛, current-gain cutoff frequency (fT) of 738 GHz, and maximum oscillation frequency (fmax) of 492 GHz. The results indicate that the reduction of Lg to 19 nm improves the DC and RF characteristics of InGaAs HEMTs, and a possible increase in the parasitic capacitance component, associated with T-shap, remains negligible in the device architecture.

Study of monolithic 3D integrated-circuit consisting of tunneling field-effect transistors (터널링 전계효과 트랜지스터로 구성된 3차원 적층형 집적회로에 대한 연구)

  • Yu, Yun Seop
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.26 no.5
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    • pp.682-687
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    • 2022
  • In this paper, the research results on monolithic three-dimensional integrated-circuit (M3DICs) stacked with tunneling field effect transistors (TFETs) are introduced. Unlike metal-oxide-semiconductor field-effect transistors (MOSFETs), TFETs are designed differently from the layout of symmetrical MOSFETs because the source and drain of TFET are asymmetrical. Various monolithic 3D inverter (M3D-INV) structures and layouts are possible due to the asymmetric structure, and among them, a simple inverter structure with the minimum metal layer is proposed. Using the proposed M3D-INV, this M3D logic gates such as NAND and NOR gates by sequentially stacking TFETs are proposed, respectively. The simulation results of voltage transfer characteristics of the proposed M3D logic gates are investigated using mixed-mode simulator of technology computer aided design (TCAD), and the operation of each logic circuit is verified. The cell area for each M3D logic gate is reduced by about 50% compared to one for the two-dimensional planar logic gates.

Priority Analysis of Climate Smart Agriculture (CSA) Technology using Analytic Hierarchy Process (AHP) (계층화 분석기법(AHP)을 이용한 기후스마트농업(CSA) 기술의 우선순위 분석)

  • HyunJi Lee;KyungJae Lee;Sung Eun Sally Oh;Yun Yeong Choi;Brian H.S. Kim
    • Journal of Korean Society of Rural Planning
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    • v.28 no.4
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    • pp.127-138
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    • 2022
  • In responding to climate change in the agricultural sector, Climate Smart Agriculture (CSA) is an approach to establish a sustainable agricultural system through comprehensive management of technology, policy, and investment. The international community is continually expanding CSA implementation, and it became more important to understand the status of the domestic agriculture system and practices that are relevant to CSA. This study explored the available CSA in domestic agricultural systems and presented the order of relative importance of CSA technology. AHP analysis is employed for the evaluation with the following criteria: productivity, marketability, adaptability, and mitigation. The relative importance is evaluated with six agricultural technologies (soil, crop management, water, energy efficiency, alternative energy, and precision agriculture) in 28 agricultural technology sectors. The results of the AHP analysis showed that 'alternative energy' was found to be a top priority among the agricultural technology sectors, and 'shallow depth drain in rice paddy' was a top priority for agricultural technology. Also, the 'marketability' in soil and water sectors, 'mitigation' in crop management, and 'adaptability' in energy efficiency and alternative energy were given higher priority. The results of this study can be used as a good source for strategic CSA preparation and application.

Electron transport in core-shell type fullerene nanojunction

  • Sergeyev, Daulet;Duisenova, Ainur
    • Advances in nano research
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    • v.12 no.1
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    • pp.25-35
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    • 2022
  • Within the framework of the density functional theory combined with the method of non-equilibrium Green's functions (DFT + NEGF), the features of electron transport in fullerene nanojunctions, which are «core-shell» nanoobjects made of a combination of fullerenes of different diameters C20, C80, C180, placed between gold electrodes (in a nanogap), are studied. Their transmission spectra, the density of state, current-voltage characteristics and differential conductivity are determined. It was shown that in the energy range of -0.45-0.45 eV in the transmission spectrum of the "Au-C180-Au" nanojunction appears a HOMO-LUMO gap with a width of 0.9 eV; when small-sized fullerenes C20, C80 are intercalation into the cavity C180 the gap disappears, and a series of resonant structures are observed on their spectra. It has been established that distinct Coulomb steps appear on the current-voltage characteristics of the "Au-C180-Au" nanojunction, but on the current-voltage characteristics "Au-C80@C180-Au", "Au-(C20@C80)@C180-Au" these step structures are blurred due to a decrease in Coulomb energy. An increase in the number of Coulomb features on the dI/dV spectra of core-shell fullerene nanojunctions was revealed in comparison with nanojunctions based on fullerene C60, which makes it possible to create high-speed single-electron devices on their basis. Models of single-electron transistors (SET) based on fullerene nanojunctions "Au-C180-Au", "Au-C80@C180-Au" and "Au-(C20@C80)@C180-Au" are considered. Their charge stability diagrams are analyzed and it is shown that SET based on C80@C180-, (C20@C80)@C180- nanojunctions is output from the Coulomb blockade mode with the lowest drain-to-source voltage.

Potential clinical utility of intraoperative fluid amylase measurement during pancreaticoduodenectomy

  • Kunal Joshi;Manuel Abradelo;David Christopher Bartlett;Nikolaos Chatzizacharias;Bobby Venkata Dasari;John Isaac;Ravi Marudanayagam;Darius Mirza;Keith Roberts;Robert Peter Sutcliffe
    • Annals of Hepato-Biliary-Pancreatic Surgery
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    • v.27 no.2
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    • pp.189-194
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    • 2023
  • Backgrounds/Aims: Postoperative pancreatic fistula (POPF) after pancreaticoduodenectomy (PD) is a source of major morbidity and mortality. Early diagnosis and treatment of POPF is mandatory to improve patient outcomes and clinical risk scores may be ombined with postoperative drain fluid amylase (DFA) values to stratify patients. The aim of this pilot study was to etermine if intraoperative fluid amylase (IFA) values correlate with DFA1 and POPF. Methods: In patients undergoing PD from February to November 2020, intraoperative samples of intra-abdominal fluid adjacent to the pancreatic anastomosis were taken and sent for fluid amylase measurement prior to abdominal closure. Data regarding patient demographics, postoperative DFA values, complications, and mortality were prospectively collected. Results: Data were obtained for 52 patients with a median alternative Fistula Risk Score (aFRS) of 9.9. Postoperative complications occurred in 20 (38.5%) patients (five Clavien grade ≥ 3). There were eight POPFs and two patients died (pneumonia/sepsis). There was a significant correlation between IFA and DFA1 (R2 = 0.713; p < 0.001) and DFA3 (p < 0.001), and the median IFA was higher in patients with POPF than patients without (1,232.5 vs. 122; p = 0.0003). IFA > 260 U/L predicted POPF with sensitivity, specificity, positive and negative predictive values of 88.0%, 75.0%, 39.0%, and 97.0%, respectively. The incidence of POPF was 43.0% in high-risk (high aFRS/IFA) and 0% in lowrisk patients (low aFRS/IFA). Conclusions: IFA correlated with POPF and may be a useful adjunct to clinical risk scores to stratify patients during PD. Larger, prospective studies are needed to determine whether IFA has clinical utility.

Millimeter-wave Broadband Amplifier integrating Shunt Peaking Technology with Cascode Configuration (Cascode 구조에 Shunt Peaking 기술을 접목시킨 밀리미터파 광대역 Amplifier)

  • Kwon, Hyuk-Ja;An, Dan;Lee, Mun-Kyo;Lee, Sang-Jin;Moon, Sung-Woon;Baek, Tae-Jong;Park, Hyun-Chang;Rhee, Jin-Koo
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.43 no.10 s.352
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    • pp.90-97
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    • 2006
  • We report our research work on the millimeter-wave broadband amplifier integrating the shunt peaking technology with the cascode configuration. The millimeter-wave broadband cascode amplifier on MIMIC technology was designed and fabricated using $0.1{\mu}m\;{\Gamma}-gate$ GaAs PHEMT, CPW, and passive library. The fabricated PHEMT has shown a transconductance of 346.3 mS/mm, a current gain cut off frequency ($f_T$) of 113 GHz, and a maximum oscillation frequency ($f_{max}$) of 180 GHz. To prevent oscillation of designed cascode amplifier, a parallel resistor and capacitor were connected to drain of common-gate device. For expansion of the bandwidth and flatness of the gain, we inserted the short stub into bias circuits and the compensation transmission line between common-source device and common-gate device, and then their lengths were optimized. Also, the input and output stages were designed using the matching method to obtain the broadband characteristic. From the measurement, we could confirm to extend bandwidth and flat gain by integrating the shunt peaking technology with the cascode configuration. The cascode amplifier shows the broadband characteristic from 19 GHz to 53.5 GHz. Also, the average gain of this amplifier is about 6.5 dB over the bandwidth.

Circuit Performance Prediction of Scaled FinFET Following ITRS Roadmap based on Accurate Parasitic Compact Model (정확한 기생 성분을 고려한 ITRS roadmap 기반 FinFET 공정 노드별 회로 성능 예측)

  • Choe, KyeungKeun;Kwon, Kee-Won;Kim, SoYoung
    • Journal of the Institute of Electronics and Information Engineers
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    • v.52 no.10
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    • pp.33-46
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    • 2015
  • In this paper, we predicts the analog and digital circuit performance of FinFETs that are scaled down following the ITRS(International technology roadmap for semiconductors). For accurate prediction of the circuit performance of scaled down devices, accurate parasitic resistance and capacitance analytical models are developed and their accuracies are within 2 % compared to 3D TCAD simulation results. The parasitic capacitance models are developed using conformal mapping, and the parasitic resistance models are enhanced to include the fin extension length($L_{ext}$) with respect to the default parasitic resistance model of BSIM-CMG. A new algorithm is developed to fit the DC characteristics of BSIM-CMG to the reference DC data. The proposed capacitance and resistance models are implemented inside BSIM-CMG to replace the default parasitic model, and SPICE simulations are performed to predict circuit performances such as $f_T$, $f_{MAX}$, ring oscillators and common source amplifier. Using the proposed parasitic capacitance and resistance model, the device and circuit performances are quantitatively predicted down to 5 nm FinFET transistors. As the FinFET technology scales, due to the improvement in both DC characteristics and the parasitic elements, the circuit performance will improve.

Water Quality Model Development for Loading Estimates from Paddy Field (논에서의 오염부하 예측을 위한 범용모형 개발)

  • Jeon, Ji-Hong;Hwang, Ha-Sun;Yoon, Kwang-Sik;Yoon, Chun-Gyeong
    • Korean Journal of Ecology and Environment
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    • v.36 no.3 s.104
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    • pp.344-355
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    • 2003
  • Water quality model applicable paddy field was developed using field experiment during 1999 ${\sim}$ 2002. This model involves inputs from fertilization and sediment release as dirac delta function and continuous source function, respectively, and can simulate various processes such as ponded depth, surface drainage, total nitrogen concentration and total phosphorus concentration in a daily basis. The model was calibrated using data collected from field experiments which was irrigated with ground water and validated from field experiments which was irrigated with surface water. The nutrient concentration of surface water depended on the fertilization and dirac delta function can efficiently explain the valiance of nutrient concentration of surface water by fertilizer. As a result of calibration and validation, this model demonstrates good agreement. The model fit efficiencies ($R^2$) of ponded depth, surface concentration of TN and TP were 0.93,0.98 and 0.95, respectively for calibration, and those of TN and TP were 0.99 and 0.70, respectively for validation. We can apply lake and reservoir model to analysis paddy field considered with shallow ponded system, but it will need so many parameters and have much uncertainty. Fortunately, paddy field have a series of cultural practices yearly basis, such as irrigation-fertilization-forced drain-harvest with a similar time , so simple model may explain the mechanism for paddy field. Water quality model for paddy field developed in this study is simply, needs little parameters, but appeared high applicability to evaluate paddy filed drainage. We recommend this model to estimate nutrient loading from paddy field and establish best management practice.

A Study on the Design of a Beta Ray Sensor Reducing Digital Switching Noise (디지털 스위칭 노이즈를 감소시킨 베타선 센서 설계)

  • Kim, Young-Hee;Jin, Hong-Zhou;Cha, Jin-Sol;Hwang, Chang-Yoon;Lee, Dong-Hyeon;Salman, R.M.;Park, Kyung-Hwan;Kim, Jong-Bum;Ha, Pan-Bong
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.13 no.5
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    • pp.403-411
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    • 2020
  • Since the analog circuit of the beta ray sensor circuit for the true random number generator and the power and ground line used in the comparator circuit are shared with each other, the power generated by the digital switching of the comparator circuit and the voltage drop at the ground line was the cause of the decreasein the output signal voltage drop at the analog circuit including CSA (Charge Sensitive Amplifier). Therefore, in this paper, the output signal voltage of the analog circuit including the CSAcircuit is reduced by separating the power and ground line used in the comparator circuit, which is the source of digital switching noise, from the power and ground line of the analog circuit. In addition, in the voltage-to-voltage converter circuit that converts VREF (=1.195V) voltage to VREF_VCOM and VREF_VTHR voltage, there was a problem that the VREF_VCOM and VREF_VTHR voltages decrease because the driving current flowing through each current mirror varies due to channel length modulation effect at a high voltage VDD of 5.5V when the drain voltage of the PMOS current mirror is different when driving the IREF through the PMOS current mirror. Therefore, in this paper, since the PMOS diode is added to the PMOS current mirror of the voltage-to-voltage converter circuit, the voltages of VREF_VCOM and VREF_VTHR do not go down at a high voltage of 5.5V.