참고문헌
- Frank, M.M., "High-k/metal gate innovations enabling continued CMOS scaling," 2011 Proceedings of ESSCIRC (ESSCIRC), pp. 50-58, Sept. 2011.
- Ran Liu, "Process characterization for strained Si on SOI CMOS devices," Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference, pp. 138-141, Oct. 2008.
- Jyh-Chyurn Guo, "Halo and LDD Engineering for Multiple VTH High Performance Analog CMOS Devices," IEEE Trans. Semiconductor Manufacturing, vol. 20, no. 3, pp. 313 - 322, Aug. 2007. https://doi.org/10.1109/TSM.2007.901408
- James D., "Intel Ivy Bridge unveiled - The first commercial tri-gate, high-k, metal-gate CPU," Custom Integrated Circuits Conference (CICC), pp. 1-4, Sept. 2012.
- Auth C., Allen C., Blattner A. et al., "A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors," VLSI Technology (VLSIT), pp. 131-132, June. 2012.
-
Natarajan S., Agostinelli M., Akbar S. et al., "A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588
${\mu}m2$ SRAM cell size," VLSI Technology (VLSIT), pp. 131-132, June. 2012. -
Yen-Huei C., Wei-Min C., Wei-Cheng W., et al., "A 16nm 128Mb SRAM in high-
$\kappa$ metal-gate FinFET technology with write-assist circuitry for low-VMIN applications," Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 238-239, Feb. 2014. - Amat E., Canal R., et al., "Variability robustness enhancement for 7nm FinFET 3T1D-DRAM cells," IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 81 - 84, Aug. 2013.
- Lee K., An T., Joo S., Kwon K.-W., Kim S., "Modeling of parasitic fringing capacitance in multifin trigate FinFETs." Electron Devices, IEEE Transactions, vol. 60, no. 5, pp. 1786-1789, 2013. https://doi.org/10.1109/TED.2013.2252467
- SeokSoon Noh, KeeWon Kwon, and SoYoung Kim, "Analysis of Process and Layout Dependent Analog Performance of FinFET Structure using 3D Device Simulator," The Journal of The Institute of Electrical Engineers of Korea, vol. 50, no. 4, pp. 795-802, April. 2013.
- An, TaeYoon, et al. "Performance Optimization Study of FinFETs Considering Parasitic Capacitance and Resistance." Journal of semiconductor technology and science, vol. 14, no. 5, pp. 525-536, 2014. https://doi.org/10.5573/JSTS.2014.14.5.525
- Choe, Kyeungkeun, TaeYoon An, and SoYoung Kim., "Accurate fringe capacitance model considering RSD and metal contact for realistic FinFETs and circuit performance simulation." Simulation of Semiconductor Processes and Devices (SISPAD), pp. 29 - 32, Sept. 2014.
- Lacord J., Ghibaudo G., and Boeuf F., "Comprehensive and Accurate Parasitic Capacitance Models for Two - and Three-Dimensional CMOS Device Structures." IEEE Trans. Electron Devices, vol. 59, no. 5, pp. 1332-1344, April. 2012. https://doi.org/10.1109/TED.2012.2187454
- Bansal A., Paul B.C., Roy K., "An Analytical Fringe Capacitance Model for Interconnects Using Conformal Mapping" IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 12, pp. 2765 - 2774, Nov. 2006. https://doi.org/10.1109/TCAD.2006.882489
- Bansal A., Paul B.C., Roy K., "Modeling and optimization of fringe capacitance of nanoscale DGMOS devices." IEEE Trans. Electron Devices, vol. 52, no. 2, pp. 256-262, Jan. 2005. https://doi.org/10.1109/TED.2004.842713
- Ivanov, Valentin I., and Michael K. Trubetskov. Handbook of conformal mapping with computer-aided visualization. CRC press, 1994.
- Tekleab, Daniel, S. Samavedam, and P. Zeitzoff. "Modeling and analysis of parasitic resistance in double-gate FinFETs." Electron Devices, IEEE Transactions, vol. 56, no. 10, pp. 2291-2296, 2009. https://doi.org/10.1109/TED.2009.2028377
- Sohn, Chang-Woo, et al. "Analytic model of S/D series resistance in trigate FinFETs with polygonal epitaxy." Electron Devices, IEEE Transactions, vol. 60, no. 4, pp. 1302-1309, 2013. https://doi.org/10.1109/TED.2013.2246790
- TCAD Raphael User's Guide, Synopsys.
- BSIM-CMG108.0.0 Technical Manual, Aug. 2014.
- HSPICE User's Guide, Synopsys.
- The International Technology Roadmap for Semiconductors (ITRS), 2013.
- Taur, Yuan, and Tak H. Ning. Fundamentals of modern VLSI devices. Cambridge university press, 2009.
- Y. -J. Lee, T. -C. Cho, K. -H. Kao, P. -J. Sung, F. -K. Hsueh, P. -C. Huang, C. -T. Wu, S. -H. Hsu, W. -H. Huang, et al., "A novel junctionless FinFET structure with sub-5nm shell doping profile by molecular monolayer doping and microwave annealing," IEEE International Electron Devices Meeting (IEDM), pp. 32.7.1-32.7.4, Dec. 2014.
- R. -H. Baek, D. -H. Kim, T. -W. Kim, et al., "Electrostatics and performance benchmarking using all types of III-V multi-gate FinFETs for sub 7nm technology node logic application," IEEE Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers, pp. 1-2., June 2014.
- C. Binjie, A. -R. Brown, W. Xingsheng, and A. Asenov "Statistical variability study of a 10nm gate length SOI FinFET device," 2012 Silicon Nanoelectronics Workshop (SNW), pp. 1-2, June 2012.
- W. -Y. Shien, C. Y. Lin, M. C. Chiang et al., "A 16nm FinFET CMOS technology for mobile SoC and computing applications," IEEE International Electron Devices Meeting (IEDM), pp. 9.1.1 - 9.1.4, Dec. 2013.
- TCAD Sentaurus User's Guide, Synopsys.
피인용 문헌
- Investigation of Electrothermal Behaviors of 5-nm Bulk FinFET vol.64, pp.12, 2017, https://doi.org/10.1109/TED.2017.2766214