• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.270-271
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• 2008

The contact resistance between organic semiconductor and source-drain electrode in Bottom Contact Organic Thin-Film Transistors (BCOTFTs) can be effectively reduced by metal oxide/molybdenum double layer structure; metal oxide layers including nickel oxide (NiOx/Mo) and moly oxide(MoOx) under molybdenum work as a high performance carrier injection layer. Step profiles of source-drain electrode can be easily achieved by simultaneous etching of the double layers using the difference etching rate between metal oxides and metal layers.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.343-343
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• 2010

In this paper, Schottky barrier thin-film-transistors (SB-TFTs) with platinum silicide at source/drain region based on glass substrate were fabricated. Poly-silicon on glass substrates was crystallized by excimer laser annealing (ELA) method. The formation of pt-silicide at source/drain region is the most important process for SB-TFTs fabrication. We study the optimal condition of Pt-silicidation on glass substrate. Also, we propose this device as promising structure in the future.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2006.05a
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• pp.591-592
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• 2006

We studied about the manufacture of the drain-source contacts for OTFTs(organic thin-film transistors) by using screen printing method. The conductive fillers used Ag and carbon black. The conductive contacts with $100{\mu}m$ of channel length were screen printed on a silicon dioxide gate dielectric layer and, the pentacene semiconductor was deposited via vacuum deposition. As a result of studying various conductive pastes, we could obtain the OTFTs which exhibited field-effect behavior over arrange of drain-source and gate voltages, similar to devices employing deposited Au contacts. By using screen-printing with conductive paste, the contacts are processed at low temperature, thereby facilitating their integration with heat sensitive substrates.

• Proceeding of EDISON Challenge
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• 2016.03a
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• pp.285-287
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• 2016

이황화 몰리브덴(Molybdenum disulfide: $MoS_2$)을 채널(Channel) 물질로 이용하여 metal-oxide-semiconductor(MOS) 구조를 제작하고, 효율적인 제작과정을 제시하였고 특히, Source/Drain의 Doping concentration을 조절하여 효과적인 $MoS_2$ Transistor를 제작 및 시뮬레이션 하였다. 그 후 여러 MOSFET의 특성 분석을 통하여 소자로서의 기능을 확인해보았다. 그리고 특히 채널의 전기적인 특성을 분석하고 채널 내 그리고 contact 사이의 저항 및 mobility의 특성을 알아보았는데, 그 중 Source/Drain Doping Effect와 performance 분석을 통해, 최적화된 $MoS_2$ Transistor를 찾아보았다.

• Transactions on Electrical and Electronic Materials
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• v.7 no.4
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• pp.180-183
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• 2006

We report for the first time two-bit operational characteristics of a high-density NOR-type polysilicon-oxide-nitride-oxide-silicon (SONOS) array with common source line (CSL). An undesired disturbance, especially drain disturbance, in the NOR array with CSL comes from the two-bit-per-cell operation. To solve this problem, we propose an efficient bulk-biased programming technique. In this technique, a bulk bias is additionally applied to the substrate of memory cell for decreasing the electric field between nitride layer and drain region. The proposed programming technique shows free of drain disturbance characteristics. As a result, we have accomplished reliable two-bit SONOS array by employing the proposed programming technique.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.6
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• pp.457-461
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• 2009

In this paper, barrier height between Ni-silicide and source/drain is reduced utilizing Pd stacked structure (Pd/Ni/TiN) for high performance PMOSFET. It is shown that the barrier height is decreased by Pd incorporation and is dependent on the Pd thickness. Therefore, Ni-silicide using the Pd stacked structure is promising for high performance nano-cale PMOSFET.

• Journal of Advanced Marine Engineering and Technology
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• v.32 no.8
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• pp.1263-1268
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• 2008

In this paper, the low noise power amplifier for GaAs FET ATF-10136 is designed and fabricated with active bias circuit and self bias circuit. To supply most suitable voltage and current, active bias circuit is designed. Active biasing offers the advantage that variations in the pinch-off voltage($V_p$) and saturated drain current($I_{DSS}$) will not necessitate a change in either the source or drain resistor value for a given bias condition. The active bias network automatically sets a gate-source voltage($V_{gs}$) for the desired drain voltage and drain current. Using resistive decoupling circuits, a signal at low frequency is dissipated by a resistor. This design method increases the stability of the LNA, suitable for input stage matching and gate source bias. The LNA is fabricated on FR-4 substrate with active and self bias circuit, and integrated in aluminum housing. As a results, the characteristics of the active and self bias circuit LNA implemented more than 13 dB and 14 dB in gain, lower than 1 dB and 1.1 dB in noise figure, 1.7 and 1.8 input VSWR at normalized frequency $1.4{\sim}1.6$, respectively.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.10
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• pp.885-888
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• 2008

We present simulation results on DC characteristics of AlGaN/GaN HEMTs having trench shaped source/drain Ohmic electrodes. In order to reduce the contact resistance in the source and drain region of the conventional AlGaN/GaN HEMTs and thereby to increase their DC output power, we applied narrow-shaped-trench electrode schemes whose size varies from $0.5{\mu}m$ to $1{\mu}m$ to the standard AlGaN/GaN HEMT structure. As a result, we found that the drain current was increased by 13 % at the same gate bias condition and the transconductance (gm) was improved by 11 % for the proposed AlGaN/GaN HEMT, compared with those of the conventional AlGaN/GaN HEMTs.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.3
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• pp.136-147
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• 2009

In this paper we analyze the influence of source/drain (S/D) extension region design for minimizing short channel effects (SCEs) in 25 nm gate length single and double gate Silicon-on-Insulator (SOI) and Germanium-on-Insulator (GOI) MOSFETs. A design methodology, by evaluatingm the ratio of the effective channel length to the natural length for the different devices (single or double gate FETs) and technology (SOI or GOI), is proposed to minimize short channel effects (SCEs). The optimization of non-overlapped gate-source/drain i.e. underlap channel architecture is extremely useful to limit the degradation in SCEs caused by the high permittivity channel materials like Germanium as compared to that exhibited in Silicon based devices. Subthreshold slope and Drain Induced Barrier Lowering results show that steeper S/D gradients along with wider spacer regions are needed to suppress SCEs in GOI single/double gate devices as compared to Silicon based MOSFETs. A design criterion is developed to evaluate the minimum spacer width associated with underlap channel design to limit SCEs in SOI/GOI MOSFETs.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.7A
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• pp.451-466
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• 2003

Untethered nodes in mobile ad-hoc networks strongly depend on the efficient use of their batteries. In this paper, we propose a new metric, the drain rate, to forecast the lifetime of nodes according to current traffic conditions. This metric is combined with the value of the remaining battery capacity to determine which nodes can be part of an active route. We describe new route selection mechanisms for MANET routing protocols, which we call the Minimum Drain Rate (MDR) and the Conditional Minimum Drain Rate (CMDR). MDR extends nodal battery life and the duration of paths, while CMDR also minimizes the total transmission power consumed per packet. Using the ns-2 simulator and the dynamic source routing (DSR) protocol, we compare MDR and CMDR against prior proposals for power-aware routing and show that using the drain rate for power-aware route selection offers superior performance results.