Journal of the Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회논문지)

The Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회)
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Reduction of Barrier Height between Ni-silicide and p+ Source/drain for High Performance PMOSFET

고성능 PMOSFET을 위한 Ni-silicide와 p+ Source/drain 사이의 Barrier Height 감소

  • Published : 2009.06.01
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Abstract

In this paper, barrier height between Ni-silicide and source/drain is reduced utilizing Pd stacked structure (Pd/Ni/TiN) for high performance PMOSFET. It is shown that the barrier height is decreased by Pd incorporation and is dependent on the Pd thickness. Therefore, Ni-silicide using the Pd stacked structure is promising for high performance nano-cale PMOSFET.

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References

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