• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2006.11a
• /
• pp.149-150
• /
• 2006

A ZnO nanowire-based FET is fabricated m this study on a flexible substrate of PES. For the flat and bent flexible substrates, the current ($I_D$) versus drain-source bias voltage ($V_{DS}$) and $I_D$ versus gate voltage ($V_G$) results are compared. The flat band was Ion/Ioff ratio of ${\sim}10^7$, a transconductance of 179 nS and a mobility of ~10.104 cm2/Vs at $V_{DS}$ =1 V. Also bent to a radius curvature of 0.15cm and experienced by an approximately strain of 0.77 % are exhibited an Ion/Ioff ratio of ${\sim}10^7$, a transconductance of ~179 nS and a mobility of ${\sim}10.10 cm^2/Vs$ at $V_{DS}$ = 1V. The electrical characteristics of the FET are not changed very much. although the large strain is given on the device m the bent state.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.3 s.333
• /
• pp.1-8
• /
• 2005

In this paper, we analyzed the DC and RF characteristics of $0.1\;{\mu}m$ metamorphic high electron mobility transistor (MHEMT) using the ISE-TCAD simulation tool. we also analyzed the effects or the scaling on vertical and lateral dimensions such as a gate length, source-drain spacing, and channel thickness. We discussed the degradation of extrinsic transconductance $g_{m,max}$ in the MHEMTs adopting the gate length $(L_g)$ of $sub-0.1\;{\mu}m$. We suggested the model describing the effects on the vertical and lateral parameter scaling.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2008.10a
• /
• pp.1203-1207
• /
• 2008

For a large sized, ultra definition (UD) and high refresh rate for motion blur free AMLCD TVs, amorphous IGZO thin film transistor (TFT) are applied and investigated in terms of threshold voltage ($V_{th}$) shift influenced by active layer thickness uniformity, source drain etching technology, heat treatment and passivation condition. Optimizing above parameters, we fabricated the world's largest 15 inch XGA AMLCD successfully.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2006.08a
• /
• pp.1174-1177
• /
• 2006

A bottom contact organic thin film transistor (OTFT) is fabricated with an organic double-layered gate insulator (GI) and pentacene. The PMMA and MNB layers are treated on gate insulator and source/drain (S/D, Au) before depositing pentacene to investigate device properties and pentacene growth. The sequence of surface treatment affects a device performance seriously. The ultra-thin PMMA (below 50A) was deposited on organic gate insulator and S/D metal by spin coating method, which showed no deterioration of on-state current (Ion) although bottom contact structure was exploited. We proposed that the reason of no contact resistance (Rc) increase may be due to a wettability difference in between PMMA / Au and PMMA / organic GI. As a result, the device treated by $PMMA\;{\rightarrow}\;MNB$ showed much better Ion behavior than those fabricated by $MNB\;{\rightarrow}\;PMMA$. We will report the important physical and electrical performance difference associated with surface treatment sequence.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2006.08a
• /
• pp.186-189
• /
• 2006

The flexible organic thin film transistor (OTFT) array to use as a switching device for an organic light emitting diode (OLED) was designed and fabricated in the microcontact printing and room temperature process. The gate, source, and drain electrode patterns of OTFT were fabricated by microcontact printing process. The OTFT array with dielectric layer and organic active semiconductor layer formed at room temperature or at a temperature lower than $40^{\circ}C$. The microcontact printing process using SAM and PDMS stamp made it possible to fabricate OTFT arrays with channel lengths down to even submicron size, and reduced the fabrication process by 10 steps compared with photolithography. Since the process was done in room temperature, there was no pattern shrinkage, transformation, and bending problem appeared. Also, it was possible to improve electric field mobility, to decrease contact resistance, to increase close packing of molecules by SAM, and to reduce threshold voltage by using a big dielectric.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2005.07b
• /
• pp.1364-1369
• /
• 2005

In this paper, we have identified the mechanism of C-V hysteresis behavior often observed in pentacene organic thin-film transistors (OTFTs). The capacitance-voltage (C-V) characteristics were measured for pentacene OTFTs fabricated on glass substrates with MoW as gate/source/drain electrode and TEOS $SiO_2$ as gate insulator. The measurements were made at room temperature and elevated temperatures. From the room temperature measurements, we found that the hysteresis behavior was caused by hole injection into the gate insulator from the pentacene semiconductor for large negative gate voltages, resulting in the negative flat-band voltage shift. However electron injection was observed only at elevated temperatures

• 한국정보디스플레이학회:학술대회논문집
• /
• 2003.07a
• /
• pp.675-678
• /
• 2003

We studied the electrical characteristics of pentacene-based organic field-effect transistors (FETs) with polymethyl methacrylate (PMMA) or poly-4-vinylphenol (PVP) as the gate insulator. PMMA or PVP was spin-coated on the indium tin oxide glass substrate that serves as gate electrodes. The source-drain current dependence on the gate voltage shows the FET characteristics of the hole accumulation type. The transistor with PVP shows a higher field-effect mobility of 0.14 $cm^{2}/Vs$ compared with 0.045 $cm^{2}/Vs$ for the transistor with PMMA. The atomic force microscope (AFM) images indicate that the grain size of the pentacene on PVP is larger than that on PMMA. X-ray diffraction (XRD) patterns for the pentacene deposited on PVP exhibit a new Bragg reflection at $19.5{\pm}0.2^{\circ}$, which is absent for the pentacene on PMMA. This peak corresponds to the flat-lying pentacene molecules with less intermolecular spacing.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.19 no.12
• /
• pp.1140-1143
• /
• 2006

We report on the fabrication of P3HT-based thin-film transistors (TFTs) for liquid crystal display that consist of $NiO_x$, poly-vinyl phenol (PVP), and Ni for the source-drain (S/D) electrodes, gate dielectric layer, and gate electrode, respectively The $NiO_x$ S/D electrodes of which the work function is well matched to that of P3HT are deposited on a P3HT channel by electron-beam evaporation of NiO powder. The maximum saturation current of our P3HT-based TFT is about $15{\mu}A$ at a gate bias of -30 V showing a high field effect mobility of $0.079cm^2/Vs$ in the dark, and the on/off current ratio of our TFT is about $10^5$. It is concluded that jointly adopting $NiO_x$ for the S/D electrodes and PVP for gate dielectric realizes a high-quality P3HT-based TFT.

• Transactions on Electrical and Electronic Materials
• /
• v.1 no.1
• /
• pp.40-44
• /
• 2000

Metal-ferroelectric-insulator-semoiconductor field effect transistor (MFISFETs) were fabricated using CMOS processes. The Pt/SBT/NO combined layers were etched for forming a conformal gate by using Ti/Cr metal masks and a two step etching method, By the method, we were able to fabricate a small-sized gate with the dimension of $16/4{\mu}textrm{m}$ in the width/length of gate. It has been chosen the non-self aligned source and drain implantation process, We have deposited inter-layer dielectrics(ILD) by low pressure chemical vapor deposition(LPCVD) at $380^{circ}C$ after etching the gate structure and the threshold voltage of p-channel MFISFETs were about 1.0 and -2.1V, respectively. It was also observed that the current difference between the $I_{ON}$(on current) and $I_{OFF}$(off current) that is very important in sensing margin, is more that 100 times in $I_{D}-V_{G}$ hysteresis curve.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.30 no.10
• /
• pp.665-671
• /
• 2017

Herein, we report the fabrication of low-voltage N-type organic field-effect transistors by using high capacitance fluorinated polymer gate dielectrics such as P(VDF-TrFE), P(VDF-TrFE-CTFE), and P(VDF-TrFE-CFE). Electron-withdrawing functional groups in PVDF-based polymers typically cause the depletion of negative charge carriers and a high contact resistance in N-channel organic semiconductors. Therefore, we incorporated intermediate layers of a low-k polymerto prevent the formation of a direct interface between PVDF-based gate insulators and the semiconducting active layer. Consequently, electron depletion is inhibited, and the high charge resistance between the semiconductor and source/drain electrodes is remarkably improved by the in corporation of solution-processed charge injection layers.