• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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• v.2B no.4
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• pp.207-213
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• 2002

The paper introduces a switched reluctance motor drive system based on an 80C31 and an Intel 80C 196KB single-chip microprocessor control. Advance schemes are used in turn-on and turn-off angles with the power converter's main switches during traction and regenerative braking. The principles of traction speed control and braking torque control are given. The hardware and software patterns in the 80c31 and the Intel 80C196KB single-chip microprocessor control system are also presented.

• Proceedings of the KIEE Conference
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• 1991.07a
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• pp.568-572
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• 1991

This paper describes the three-phase inverter system for 1/2[HP] induction servo motor, using TMS370C050 single-chip microprocessor. The Power MOSFETs are used for PWM inverter circuit because of the advantages such as less harmonic losses and smaller peak current, less torque ripples and noises. Single-chip microprocessor enables the whole controller to be simple and reduced size as well as to more stable and flexible. The basic structures are shown for the power circuit, including the protection and driving circuitry, and the control loops for inverter control functions. The experimental results are given for the prototype PWM inverter system.

• Proceedings of the KIEE Conference
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• 1995.07a
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• pp.303-307
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• 1995

The pulse width modulated inverters based on fully digitalized method are becoming an industrial standard. This paper describes a real time generation of fully digitalized PWM pulses and its realization by single chip microprocessor. To verify the effectiveness of the proposed technique, the algorithm is implemented by using single chip microprocessor, 8097BH. The proposed method is compared with the well known triangular comparison method through experimental results, and the speed control of a motor is experimentally done by voltage-to-frequency constant control based on the proposed PWM generation method.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.6 no.6
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• pp.49-57
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• 1992

This paper proposes a Intel 8097 single-chip microprocessor based instantaneous voltage control scheme of inverter for UPS(Uninterruptible Power Supply). There microprocessors are used to control the output voltage and frequency of the inverter, the synchronization with by-pass, and the switching of the static switch. And the status and operating conditions of UPS systems is monitored by micro processor. The inverter output voltage is controlled instantaneously with a double regulation loop so that it has very good dynamic response for the varying loads or nonlinear loads as a rectifier. And also, the software and hardware of control system is described. From simulation and experimental results, it is shown that the proposed scheme has very good performance.

• Journal of the Korean Professional Engineers Association
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• v.33 no.4
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• pp.53-58
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• 2000

Within 10years, it will be possible to integrate 10B transistors on a single chip microprocessor which wilt operate far beyond GHZ, and it will execute about 20-200 instructions per clock cycle from widely variable instruction streams leveraging SMT(Simultaneous Multithreading) technology . Also it will decouple the current legacy X86 binary compatibility by translation layer such as code morphing technology.

• Journal of Ocean Engineering and Technology
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• v.11 no.1
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• pp.106-112
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• 1997

This paper describes the development of a test-bed vehicle named TAUV which can be a tool to evaluate the performance of a new control algorithm, operating software and the characteristics of sensors for an AUV. The test-bed AUV is designed to operate at depth of ten meters. It is 19.5kg in air and neural buoyancy in water and the dimension is $535{\times}400{\times}102mm$. TAUV is equipped with a magnetic compass, a biazial inclinometer, a rate gyro, a pressure sensor and an altitude sonae for measuring the motion of the vehicle. Two horizoltal thursters and two elevators are installed in order to propel and control the AUV. This paper persents the control system of TAUV which is based on a 16 bit single-chip microprocessor, 80c196kc, and the software architecture for the operating system. Experimental results are included to verify the performance of the TAUV.

• Proceedings of the KIEE Conference
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• 1999.07g
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• pp.3233-3235
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• 1999

This paper describes development of a microprocessor-based optoelectronic guard system established a higher level of control reliability in machine guard design. The system uses the design concept of diverse redundancy and a fast software algorithm. We have accomplished an safety light curtain system that allows to be intentionally disabled moving machine by the interrupt of dangerous situations. As a result, it is showed that the proposed system is effective enough to practical applications.

• 연구논문집
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• s.24
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• pp.129-140
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• 1994

Design and implementation of monitoring and control system using dual-microprocessor node is presented for real time process. The proposed system is implemented with 2 of the single chip microprocessors in tightly coupled mode and results in speed up of $s_p=1.74.$ Under the assumption that the nodes are interconnected in multidrop. the overall system performance such as average throughout-delay characteristics and effective throughput are analyzed using M/G/1 gueueing model, and results show that the proposed node can be used to medium sized distributed monitoring and control system.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.921-924
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• 1993

For the purpose of applying to a high-speed control system, such as engine control for automobile application, we propose an architecture of a fuzzy inference processor, which can realize high-speed inference, high-resolution, and can be implemented with small chip area. We have designed a single chip based on the architecture, and confirmed the performance, such as 140 kFLIPS with 8-bit resolution.