• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
• /
• pp.261-262
• /
• 2006

High temperature superconducting coated conductor has multi-layer structure of protecting layer/superconducting layer/buffer layer/metallic substrate. The buffer layer consists of multi layer, and the architecture most widely used in RABiTS approach is $CeO_2$(cap layer)/YSZ(diffusion barrier layer)/$CeO_2$(seed layer). Multi-buffer layer deposition required many times and process. Therefore single buffer layer deposition study reduce 2G HTS manufacture efforts. Evaporation technique for single buffer deposition method is used for the $CeO_2$ layer. $CeO_2$ single buffer film could be achieved in the chamber. Detailed deposition conditions (temperature and partial gas pressure of deposition) were investigated for the rapid growth of high quality $CeO_2$ single buffer film.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
• /
• pp.240-241
• /
• 2007

In general, high temperature superconducting coated conductors have intermediary buffers layer consisting of seed, diffusion barrier and cap layers. Simplification of the oxide materials buffer architecture in the fabrication of high temperature superconducting coated conductors is required because the deposition of multi-layers buffer architecture leads to a longer manufacturing time and a higher cost process of coated conductors. Thus, single buffer layer deposition seems to be important for practical coated conductor manufacturing process. In this study, a single gradient layered buffer deposition process of YZO for low cost coated conductors has been tried using DC reactive sputtering technique. About several thick YZO gradient single buffer layers deposited by DC co-sputtering process were found to act as a diffusion layer.

• 한국초전도ㆍ저온공학회논문지
• /
• 제8권4호
• /
• pp.8-11
• /
• 2006

High temperature superconducting coated conductor has various buffer structures on Ni-W alloy. We comparatively studied the growth conditions of a multi buffer layer $(CeO_2/YSZ/CeO_2)$ and a single buffer layer$(CeO_2)$ on textured Ni-W alloy tapes. XRD data showed that the qualities of in-plane and out-of-plane textures of the two type buffer structures were good. Also, we investigated the properties of SmBCO superconducting layer that was deposited on the two type buffer structure. The SmBCO superconducting properties on the single and multi buffer structure showed different critical current values and surface morphologies. FWHM of In-plane and out-of-plane textures were $7.4^{\circ},\;5.0^{\circ}$ in the top CeO2 layer of the multi-buffer layers of $CeO_2/YSZ/CeO_2$, and $7.3^{\circ},\;5.1^{\circ}$ in the $CeO_2$ single buffer layer. $1{\mu}m-thick$ SmBCO superconducting layers were deposited on two type buffer layer. $I_c$ of SmBCO deposited on single and multi buffer were 90 A/cm, 150 A/cm and corresponding $J_c$ were $0.9MA/cm^2,\;1.5MA/cm^2$ at 77K in self-field, respectively.

• 대한전자공학회논문지TC
• /
• 제40권10호
• /
• pp.95-102
• /
• 2003

광 전송 네트워크의 스위칭 기술에서 자원 충돌 문제를 해결하기 위한 방법으로 버퍼링은 중요한 문제중 하나이다. 본 논문은 가변길이 광 패킷 스위칭에 있어서 Fiber Delay Line(FDL)을 사용한 광 버퍼의 dimensioning과 패킷의 손실률에 대하여 연구하였다. 우선 단단(single-stage) FDL 버퍼에서의 granularity와 버퍼 손실에 대한 관계를 고찰하고 간단한 구조의 다단(multi-stage) FDL 버퍼 구조를 제안하였다. 다단 FDL 버퍼는 구현 기술이나 경제성의 측면에서 현 시점에서는 실용성이 높지 않지만 본 논문에서는 미래에 실용화가 가능할 것이라는 가정 하에 다단 FDL 버퍼 구조들을 제안한다. 제안한 FDL 버퍼 구조에서 각 스테이지에 사용되는 지연 및 패스 라인의 소요량을 시뮬레이션을 통해 고찰하고 그 사용율에 근거하여 multi-stage FDL 버퍼를 dimensioning하였다. 또한 보다 실질적인 구조의 다단(multi-stage) FDL 버퍼를 제안하고 그 적합성을 버퍼 크기와 패킷 손실율의 관계를 통하여 연구하였다.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
• /
• pp.180-181
• /
• 2006

As a rule, high temperature superconducting coated conductors have multi-layered buffers consisting of seed, diffusion barrier and cap layers. Multi-buffer layer deposition requires longer fabrication time. This is one of main reasons which increases fabrication cost Thus, single buffer layer deposition seems to be important for practical coated conductor process. In this study, a single layered buffer deposition of $CeO_2$ for low cost coated conductors has been tried using thermal evaporation technique 100nm-thick $CeO_2$ layers deposited by thermal evaporation were found to act as a diffusion layer. $0.4{\mu}m$-thick SmBCO superconducting layers were deposited by thermal co-evaporation on the $CeO_2$ buffered Ni-W substrate. Critical current of 118A/$cm^2$ was obtained for the SmBCO coated conductors.

• 한국전기전자재료학회논문지
• /
• 제20권6호
• /
• pp.546-549
• /
• 2007

As a rule, high temperature superconducting coated conductors have multi-layered buffers consisting of seed, diffusion barrier and cap layers. Multi-buffer layer deposition requires longer fabrication time. This is one of main reasons which increases fabrication cost. Thus, single buffer layer deposition seems to be important for practical coated conductor process. In this study, a single layered buffer deposition of $CeO_2$ for low cost coated conductors has been tried using thermal evaporation technique. 100 nm-thick $CeO_2$ layers deposited by thermal evaporation were found to act as a diffusion layer. $1\;{\mu}m-thick$ SmBCO superconducting layers were deposited by thermal co-evaporation on the $CeO_2$ buffered Ni-5%W substrate. Critical current of 90 A/cm was obtained for the SmBCO coated conductors.

• Journal of Information Display
• /
• 제12권1호
• /
• pp.61-67
• /
• 2011

A single-clock-driven shift register and a two-stage buffer are proposed, using p-type, low-temperature polycrystalline silicon thin-film transistors. To eliminate the clock skew problems and to reduce the burden of the interface, only one clock signal was adopted to the shift register circuit, without additional reference voltages. A two-stage, p-type buffer was proposed to drive the gate line load and shows a full-swing output without threshold voltage loss. The shift register and buffer were designed for the 3.31" WVGA ($800{\times}480$) LCD panel, and the fabricated circuits were verified via simulations and measurements.

• 한국초전도ㆍ저온공학회논문지
• /
• 제6권4호
• /
• pp.41-45
• /
• 2004

Rapid Single flux quantum (RSFQ) confluence buffer is widely used in complex superconductive digital circuits. In this work, we have improved the currently used confluence buffer and obtained a more soundly designed confluence buffer. In simulations, improvements in the bias margins of 11 % and the global margins of 10%, compared to the previously used confluence buffer, were achieved. Global margins are very important in estimating a process error range allowed in fabrications. We used two circuit simulation tools, WRspice and Julia, to design and optimize the confluence buffer. We used Xic to obtain a mask layout. We fabricated the improved circuits by using Nb technology. The test results at low frequency showed that the improved confluence buffer operated correctly and had a very wide main bias margin of +/-43% enhanced from +/-26% of the previously used confluence buffer.

• 열처리공학회지
• /
• 제28권6호
• /
• pp.291-295
• /
• 2015

IGZO single layer and $IGZO/TiO_2$ bi-layered films were deposited on glass substrate at room temperature with radio frequency magnetron sputtering to investigate the effect of $TiO_2$ buffer layer on the electrical and optical properties of the films. For all deposition, the thickness of IGZO and $TiO_2$ Buffer layer was kept at 100 and 5 nm, respectively. In a comparison of figure of merit, IGZO films with a 5-nm-thick $TiO_2$ buffer layer show the higher figure of merit ($8.40{\times}10^{-5}{\Omega}^{-1}$) than that of the IGZO single layer films ($6.23{\times}10^{-5}{\Omega}^{-1}$) due to the enhanced optical transmittance and the decreased sheet resistance of the films. The observed results mean that a 5 nm thick $TiO_2$ buffer layer in the $IGZO/TiO_2$ films results in better electrical and optical performance than conventional IGZO single layer films.

• Transactions on Electrical and Electronic Materials
• /
• 제14권5호
• /
• pp.242-245
• /
• 2013

Sn-doped $In_2O_3$ (ITO) thin films were prepared by radio frequency magnetron sputtering without intentional substrate heating on bare glass and $TiO_2$-deposited glass substrates to investigate the effect of a $TiO_2$ buffer layer on the electrical and optical properties of ITO films. The thicknesses of $TiO_2$ and ITO films were kept constant at 5 and 100 nm, respectively. As-deposited ITO single layer films show an optical transmittance of 75.9%, while $ITO/TiO_2$ bi-layered films show a lower transmittance of 76.1%. However, as-deposited $ITO/TiO_2$ films show a lower resistivity ($9.87{\times}10^{-4}{\Omega}cm$) than that of ITO single layer films. In addition, the work function of the ITO film is affected by the $TiO_2$ buffer layer, with the $ITO/TiO_2$ films having a higher work-function (5.0 eV) than that of the ITO single layer films. The experimental results indicate that a 5-nm-thick $TiO_2$ buffer layer on the $ITO/TiO_2$ films results in better performance than conventional ITO single layer films.