• ETRI Journal
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• v.36 no.2
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• pp.214-223
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• 2014

A fully-integrated penta-band reconfigurable power amplifier (PA) is developed for handset Tx applications. The output structure of the proposed PA is composed of the fixed output matching network, power and frequency reconfigurable networks, and post-PA distribution switches. In this work, a new reconfiguration technique is proposed for a specific band requiring power and frequency reconfiguration simultaneously. The design parameters for the proposed reconfiguration are newly derived and applied to the PA. To reduce the module size, the switches of reconfigurable output networks and post-PA switches are integrated into a single IC using a $0.18{\mu}m$ silicon-on-insulator CMOS process, and a compact size of $5mm{\times}5mm$ is thus achieved. The fabricated W-CDMA PA module shows adjacent channel leakage ratios better than -39 dBc up to the rated linear power and power-added efficiencies of higher than around 38% at the maximum linear output power over all the bands. Efficiency degradation is limited to 2.5% to 3% compared to the single-band reference PA.

• Korean Journal of Materials Research
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• v.15 no.9
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• pp.613-619
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• 2005

The ever increasing popularity and acceptance in the market place of portable systems, such as cell phones, PDA, notebook PC, etc., are fueling effects in further miniaturizing and lowering power consumption in these systems. The dynamic power consumption due to the CPU activities and the static power consumption due to leakage currents are two major sources of power consumption. Smaller devices and a lower de voltage lead to reducing the power requirement, while better insulation and isolation of devices lead to reducing leakage currents. All these can be harnessed in the SOI (silicon-on-insulator) technology. In this study, the key aspects of the SOI technology, mainly device electrical properties and device processing steps, are briefly reviewed. The interesting materials issues, such as SOI structure formation and SOI wafer fabrication methods, are then surveyed. In particular, the recent technological innovations in two major SOI wafer fabrication methods, namely wafer bonding and SIMOX, are explored and compared in depth. The results of the study are nixed in that, although the quality of the SOI structures has shown great improvements, the processing steps are still found to be too complex. Between the two methods, no clear winner has yet emerged in terms of the product quality and cost considerations.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.354-355
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• 2008

The sensitivity and sensing margin of SOI(silicon on insulator) nano-wire BioFET(field effect transistor) were investigated by using back-gate bias. The channel conductance modulation was affected by doping concentration, channel length and channel width. In order to obtain high sensitivity and large sensing margin, low doping concentration, long channel and narrow width are required. We confirmed that the electrical sensing by back-gate bias is effective method for evaluation and optimization of bio-sensor.

• Journal of the Korean institute of surface engineering
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• v.33 no.2
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• pp.101-106
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• 2000

SOI (Silicon-On-Insulator) substrates were fabricated with varying annealing temperature of $25-660^{\circ}C$ by a linear annealing method, which was modified RTA process using a linear shape heat source. The annealing method was applied to Si ∥ $SiO_2$/Si pair pre-contacted at room temperature after wet cleaning process. The bonding strength of SOI substrates was measured by two methods of Razor-blade crack opening and direct tensile test. The fractured surfaces after direct tensile test were also investigated by the optical microscope as well as $\alpha$-STEP gauge. The interface bonding energy was 1140mJ/m$^2$ at the annealing temperature of $430^{\circ}C$. The fracture strength was about 21MPa at the temperature of $430^{\circ}C$. These mechanical properties were not reported with the conventional furnace annealing or rapid thermal annealing method at the temperature below $500^{\circ}C$. Our results imply that the bonded wafer pair could endure CMP (Chemo-Mechanical Polishing) or Lapping process without debonding, fracture or dopant redistribution.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.533-533
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• 2007

The stress effect of SiGe p-type metal oxide semiconductors field effect transistors(MOSFETs) has been investigated to compare device properties using Si bulk and partially depleted silicon on insulator(PD SOI). The electrical properties in SiGe PD SOI presented enhancements in subthreshold slope and drain induced barrier lowering in comparison to SiGe bulk. The reliability of gate oxides on bulk Si and PD SOI has been evaluated using constant voltage stressing to investigate their breakdown (~ 8.5 V) characteristics. Gate leakage was monitored as a function of voltage stressing time to understand the breakdown phenomena for both structures. Stress induced leakage currents are obtained from I-V measurements at specified stress intervals. The 1/f noise was observed to follow the typical $1/f^{\gamma}$ (${\gamma}\;=\;1$) in SiGe bulk devices, but the abnormal behavior ${\gamma}\;=\;2$ in SiGe PD SOI. The difference of noise frequency exponent is mainly attributed to traps at silicon oxide interfaces. We will discuss stress induced instability in conjunction with the 1/f noise characteristics in detail.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.146-146
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• 2010

일반적인 MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor)은 소스와 드레인의 형성을 위해서 불순물을 주입하고 고온의 열처리 과정을 거치게 된다. 이러한 고온의 열처리 과정 때문에 녹는점이 낮은 메탈게이트와 게이트 절연막으로의 high-k 물질의 사용에 제한을 받게된다. 이와 같은 문제점을 보완하기 위해서 소스와 드레인 영역에 불순물 주입공정 대신에 금속접합을 이용한 Schottky Barrier Tunnel Transistor (SBTT)가 제안되었다. SBTT는 $500^{\circ}C$ 이하의 저온에서 불순물 도핑없이 소스와 드레인의 형성이 가능하며 실리콘에 비해서 수십~수백배 낮은 면저항을 가지며, 단채널 효과를 효율적으로 제어할 수 있는 장점이 있다. 또한 고온공정에 치명적인 단점을 가지고 있는 high-k 물질의 적용 또한 가능케한다. 본 연구에서는 p-type SOI (Silicon-On-Insulator) 기판을 이용하여 Pt-silicide 소스와 드레인을 형성하고 전기적인 특성을 분석하였다. 또한 본 연구에서는 기존의 sidewall을 사용하지 않는 새로운 구조를 적용하여 메탈게이트의 사용을 최적화하였고 게이트 절연막으로써 실리콘 옥사이드를 스퍼터링을 이용하여 증착하였기 때문에 저온공정을 성공적으로 수행할 수 있었다. 이러한 게이트 절연막은 열적으로 형성시키지 않고도 70 mv/dec 대의 우수한 subthreshold swing 특성을 보이는 것을 확인하였고, $10^8$정도의 높은 on/off current ratio를 갖는 것을 확인하였다.

• Journal of Sensor Science and Technology
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• v.16 no.2
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• pp.126-131
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• 2007

In this paper, we fabricated piezoresistive pressure sensor with dry etching technology which used ICP-RIE (inductively coupled plasma reactive ion etching) and etching delay technology which used SOI (silicon-on-insulator). Structure of the fabricated pressure sensor shows a square diaphragm connected to a frame which was vertically fabricated by dry etching process and a single-element four-terminal gauge arranged at diaphragm edge. Sensitivity of the fabricated sensor was about 3.5 mV/V kPa at 1 kPa full-scale. Measurable resolution of the sensor was not exceeding 20 Pa. The nonlinearity of the fabricated pressure sensor was less than 0.5 %F.S.O. at 1 kPa full-scale.

• Proceedings of the KIEE Conference
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• 2003.07c
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• pp.1912-1913
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• 2003

This paper presents a variable optical attenuator (VOA) that is fabricated using bosch deep silicon etching process [1] with silicon-on- insulator (SOI) wafer. The VOA consists of driving electrode, ground electrode, actuating mirror, and mechanical slower. In this VOA, actuating mirror is driven by electrostatic force [2] and the pull-in voltage is close to 13V, 28 V, 46V come along with the spring width of $3{\mu}m,\;5{\mu}m,\;7{\mu}m$ respectively.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.1
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• pp.179-184
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• 1995

Phosphorous was deped in silicon thin films by Ion Mass Doping and Changes in the electrical resistance with respect tko heat treatments were investigated. SOI(Silicon On Insulator) thin films which contain few grain boundaries prepared by ZMR(Zone Melting Recrystallization) of polysilicon films, polysilicon films which have about 1500 $A^{\rarw}$ of grain size prepared by LPCVD at 625.deg. C, and amorphous silicon thin films prepared by LPCVD at low temperature were used as substrates and thermal behavior of phosphorous after RTA(Rapid Thermal Annealing) and furnace annealing was carefully studied. Amorphous thin films showed about 10$^{6}$ .OMEGA./ㅁbefore any heat treatment, while polycrystalline and SOI films about 10$^{3}$.OMEGA./¤. All these films, however, showed about 10.OMEGA./ㅁafter furnace annealing at 700.deg. C for 3hrs and RTA showed about the same trend. Films with grain boundaries showed a certain range of heat treatment which rendered increase of the electrical resistance upon annealing, which could not be observed in amorphous films and segregation of doped phosphorous by diffusion with annealing was thought to be responsible for this abnormal behavior.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.2
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• pp.102-109
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• 2007

We propose and experimentally demonstrate a ring resonator with sharp U-turns fabricated on a silicon-on-insulator (SOI) substrate; the resonator was designed as a key part of an optical, dynamic data storage device. We discuss the optical properties of the fabricated ring resonator from the viewpoint of equi-frequency-contour behavior in a dispersion space. We successfully characterize its optical characteristics on the basis of photonic crystal physics. It is suggested that the photonic ring resonator will be applicable to optical, dynamic memory devices for optical communication systems.