• Title, Summary, Keyword: shift register

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Generalization of Galois Linear Feedback Register (갈로이 선형 궤환 레지스터의 일반화)

  • Park Chang-Soo;Cho Gyeong-Yeon
    • Journal of the Institute of Electronics Engineers of Korea CI
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    • v.43 no.1
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    • pp.1-8
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    • 2006
  • This thesis proposes Arithmetic Shift Register(ASR) which can be used as pseudo random number generator. Arithmetic Shift. Register is defined as progression that multiplies random number D , not 0 or 1 at initial value which is not 0, and it is represented as ASR-D in this thesis. Irreducible polynomial that t which makes $'D^k=1'$ satisfies uniquely as $'t=2^n-1'$ over. $GF(2^n)$ is the characteristic polynomial of ASR-D , and the cycle of Arithmetic Shift Register has maximum cycle as $'2^n-1'$. Galois Linear Feedback Shift Register corresponds to ASR-2-1. Therefore, Arithmetic Shift Register proposed in this thesis generalizes Galois Linear Feedback Shift Register. Linear complexity of ASR-D over$GF(2^n)$ is $'n{\leq}LC{\leq}\frac{n^2+n}{2}'$ and in comparison with existing Linear Feedback Shift Register stability is high. The Software embodiment of arithmetic shift register proposed in this thesis is efficient than that of existing Linear Shift Register and hardware complexity is equal. Arithmetic shift register proposed in this thesis can be used widely in various fields such as cipher, error correcting codes, Monte Carlo integral, and data communication etc along with existing linear shift register.

Operation of a High-T$_c$ Rapid Single-Flux-Quantum 4-stage Shift Register

  • Park, J.H.;Kim, Y.H.;Kang, J.H.;Hahn, T.S.;Kim, C.H.;Lee, J.M.
    • Progress in Superconductivity
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    • v.1 no.2
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    • pp.105-109
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    • 2000
  • We have designed and fabricated a single-flux-quantum(SFQ) four-stage shift register using YBCO bicrystal Josephson junctions, and tested its operations using a digital measurement set-up. The circuit consists of 4 shift register stages and a read SQUID placed next to each side of the shift register. Each SQUID was inductively coupled to the nearby shift register stage. The major obstacle in testing the circuits was the interference between the two read SQUIDs, and we could get over the problem by determining the correct operation points of the SQUID from the simultaneously measured modulation curves. Loaded data ('1' or '0') were successfully shifted from a stage to the next by a controlled current pulse injected to the bias lines located between the stages, and the corresponding correct data shifts were observed with the two read SQUIDs.

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Parallel Scrambling Techniques for Multibit-Interleaved Multiplexing Environments (다중 비트 다중화 환경에서의 병렬 혼화 기법)

  • 김석창;이병기
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.31A no.4
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    • pp.30-38
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    • 1994
  • In this paper, we propose the parallel scrambling technique which is applicable in the multibit-interleaved multiplexing environment. For this, we introduce the concept of SSRG (simple shift register generator) and MSRG(modular shift register generator), and investigate their properties. We also introduce the concept of PSRG(parallel shift register generator) - parallel form of shift register generator, and consider realizations of PSRGs based on SSRGs and MSRGs. Finally, we show how to apply PSRGs to the parallel scrambling for the SDH system.

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Bias Stability of a-IGZO TFT and a New Shift-Register Design Suitable for a-IGZO TFT (비정질 IGZO TFT의 Bias Stability 및 그에 적합한 Shift-Register 설계)

  • Lee, Young-Wook;Woo, Jong-Seok;Kim, Sun-Jae;Lee, Soo-Yeon;Han, Min-Koo
    • Proceedings of the KIEE Conference
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    • pp.1424-1425
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    • 2011
  • 비절질 IGZO TFT를 제작하여 양의 DC 및 AC에 대한 bias stability를 측정하였다. 소자특성이 상당부분 양의 방향으로 움직여 전류가 감소하였다. 따라서 기존의 Shift-Register는 양의 스트레스 전압을 지속적으로 받기 때문에 회로가 제대로 동작하지 않을 수 있다. 따라서 우리는 양의 스트레스 전압을 받지않는 새로운 Shift-register를 고안하고 SPICE 시뮬레이션을 통하여 안정한 출력을 확인하였다.

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Design of Radiation Hardened Shift Register and SEU Measurement and Evaluation using The Proton (내방사선용 Shift Register의 제작 및 양성자를 이용한 SEU 측정 평가)

  • Kang, Geun Hun;Roh, Young Tak;Lee, Hee Chul
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.8
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    • pp.121-127
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    • 2013
  • Memory devices including SRAM and DRAM are very susceptible to high energy radiation particles in the space. Abnormal operation of the devices is caused by SEE or TID. This paper presents a method to estimate proton SEU cross section representing the susceptibility of the latch circuit that the unit cell of the SRAM and proposes a new latch circuit to mitigate the SEU. 50b shift register was fabricated by using the conventional latch and the proposed latch in $0.35{\mu}m$ process. Irradiation experiment was conducted at KIRAMS by using 43MeV proton beam. It was found that the proposed latch-shift register is not affected by the radiation environment compared to the conventional latch-shift register.

Robust Two-Phase Clock Oxide TFT Shift Register over Threshold Voltage Variation and Clock Coupling Noises

  • Nam, Hyoungsik;Song, Eunji
    • ETRI Journal
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    • v.36 no.2
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    • pp.321-324
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    • 2014
  • This letter describes a two-phase clock oxide thin-film transistor shift register that executes a robust operation over a wide threshold voltage range and clock coupling noises. The proposed circuit employs an additional Q generation block to avoid the clock coupling noise effects. A SMART-SPICE simulation shows that the stable shift register operation is established for the clock coupling noises and the threshold voltage variation from -4 V to 5 V at a line time of $5{\mu}s$. The magnitude of coupling noises on the Q(15) node and Qb(15) node of the 15th stage is respectively -12.6 dB and -26.1 dB at 100 kHz in the proposed circuit, compared to 6.8 dB and 10.9 dB in a conventional one. In addition, the estimated power consumption is 1.74 mW for the proposed 16-stage shift registers at $V_{TH}=-1.56V$, compared to 11.5 mW for the conventional circuits.

Staggered Voting for TMR Shift Register Chains in Poly-Si TFT-LCDs

  • Lee, Seung-Min;Lee, In-Hwan
    • Journal of Information Display
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    • v.2 no.2
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    • pp.22-26
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    • 2001
  • This paper presents the idea of staggered voting for the efficient TMR implementation of shift register chains for improving the yield of Poly-Si TFT-LCD driving circuits. The paper discusses the characteristic features of staggered voting and performs a quantitative evaluation of its effectiveness. Staggered voting allows us to improve the reliability of a single-voter TMR chain significantly when the probability of a voter failure is not negligible.

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A single-clock-driven gate driver using p-type, low-temperature polycrystalline silicon thin-film transistors

  • Kim, Kang-Nam;Kang, Jin-Seong;Ahn, Sung-Jin;Lee, Jae-Sic;Lee, Dong-Hoon;Kim, Chi-Woo;Kwon, Oh-Kyong
    • Journal of Information Display
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    • v.12 no.1
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    • pp.61-67
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    • 2011
  • A single-clock-driven shift register and a two-stage buffer are proposed, using p-type, low-temperature polycrystalline silicon thin-film transistors. To eliminate the clock skew problems and to reduce the burden of the interface, only one clock signal was adopted to the shift register circuit, without additional reference voltages. A two-stage, p-type buffer was proposed to drive the gate line load and shows a full-swing output without threshold voltage loss. The shift register and buffer were designed for the 3.31" WVGA ($800{\times}480$) LCD panel, and the fabricated circuits were verified via simulations and measurements.

Measurements of Correct Operation of a HTS 4-bit Shift Register Circuit (4-비트 고온초전도 Shift Register 회로의 동작 측정)

  • Park, Jong-Hyeog;Kim, Young-Hwan;Kang, Joon-Hee;Hahn, Taek-Sang;Kim, Chang-Hoon;Lee, Jong-Min;Choi, Sang-Sam
    • 한국초전도학회:학술대회논문집
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    • v.9
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    • pp.102-106
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    • 1999
  • We have designed and fabricated a four-bit shift register circuit using YBCO bicrystal junctions and experimentally tested its operations by a computer-controlled digital measurement set-up. Laser ablated YBCO thin films with clean surface were used in this work. The circuit consists of the shift register and two read SQUIDs placed next to each sides of the shift register. The SQUIDs were inductively coupled to the nearby shift register stages. A probe equipped with high speed coax lines were used in this experiment. The major obstacle in testing the circuit was the interference between the read SQUIDs and we solved the problem by finding the correct operation points of the SQUIDs from the simultaneously measured modulation curves. Loaded Data("1" or "0") were successfully shifted from a stage to the next one by a controlled current pulse injected to the bias lines located between the stages and the data shifts were correctly monitored by the read SQUIDs

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