• 제목/요약/키워드: semiconductor equipment

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A experimental study about plasma ion treatment to improve hardness of electro-polished surface (전해연마면의 표면경도 향상을 위한 플라즈마 이온질화 처리법에 관한 실험적 연구)

  • Kim, Jin-Beom;Hong, Pil-Gi;Seo, Tae-Il;Son, Chang-Woo
    • Design & Manufacturing
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    • v.13 no.1
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    • pp.13-18
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    • 2019
  • The size and prospects of the domestic semiconductor equipment market are increasing every year. In the case of various parts used inside semiconductor equipments, high durability such as high strength and abrasion resistance is demanded. Particularly, the gases used in semiconductor production processes are toxic. In order to prevent such toxic gas leakage, a precision processing technique and a surface treatment technique for preventing corrosion are required. Electro-polishing is an electro-chemical method of polishing a metal surface to make it smooth and polished. Electro-polishing is mainly used in the finishing process of metal surface. Unlike mechanical polishing, electro-polishing is used in many fields, such as fine chemical etching equipment, since no damaged layer or burr, fine polishing groove and particles are generated. However, in order to withstand the gas used in the semiconductor equipment, the parts must have high corrosion resistance. However, the surface hardness generally become lowered through electro-polishing. Therefore, in this study, surface hardness were experimentally observed before and after electro-polishing. Then, a method of improving hardness by preparing a nitrided layer by plasma ion nitriding treatment.

Development of CTP Selection Methodology of Semiconductor Equipment Line Using AHP and Fuzzy Decision Model (AHP 및 Fuzzy 의사결정 모형을 활용한 반도체 장치라인의 CTP 선정 방법론 개발)

  • Jeong, Jaehwan;Kim, Jungseop;Kim, Yeojin;Lee, Jonghwan
    • Journal of the Semiconductor & Display Technology
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    • v.20 no.2
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    • pp.6-13
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    • 2021
  • Cases and studies on the selection method of CTQ are relatively active, but there are few cases or studies on the selection method of CTP which is important in the device industry. In fact, many companies simply select and manage CTP from the point of contact based on their experience and intuition. The purpose of this study is to present an evaluation model and a mathematical decision model for rational and systematic CTP selection to improve the process quality of semiconductor equipment lines. In the evaluation model, AHP (Analytic Hierarchy Process) analysis technique was applied to show objective and quantitative figures, and Fuzzy decision-making model was used to solve the ambiguity and uncertainty in the decision-making process. Decision Value (DV) was presented. The subjects were 22 process factors managed in the Plating Process that the representative equipment line can do. As a result, the evaluation model proposed in this study can support more efficient and effective decision-making for process quality improvement by more objectively measuring the problem of subjective CTP selection in manufacturing sites.

Development of Memory Controller for Punctuality Guarantee from Memory-Free Inspection Equipment using DDR2 SDRAM (DDR2 SDRAM을 이용한 비메모리 검사장비에서 정시성을 보장하기 위한 메모리 컨트롤러 개발)

  • Jeon, Min-Ho;Shin, Hyun-Jun;Jeong, Seung-Heui;Oh, Chang-Heon
    • Journal of Advanced Navigation Technology
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    • v.15 no.6
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    • pp.1104-1110
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    • 2011
  • The conventional semiconductor equipment has adopted SRAM module as the test pattern memory, which has a simple design and does not require refreshing. However, SRAM has its disadvantages as it takes up more space as its capacity becomes larger, making it difficult to meet the requirements of large memories and compact size. if DRAM is adopted as the semiconductor inspection equipment, it takes up less space and costs less than SRAM. However, DRAM is also disadvantageous because it requires the memory cell refresh, which is not suitable for the semiconductor examination equipments that require correct timing. Therefore, In this paper, we will proposed an algorithm for punctuality guarantee of memory-free inspection equipment using DDR2 SDRAM. And we will Developed memory controller using punctuality guarantee algorithm. As the results, show that when we adopt the DDR2 SDRAM, we can get the benefits of saving 13.5 times and 5.3 times in cost and space, respectively, compared to the SRAM.

A Study of Explosion Hazard Proof Modeling for Risk Minimization to Semiconductor & FPD Manufature Equipment and Clean Room (반도체·FPD 제조설비와 클린룸의 RISK 최소화를 위한 폭발위험장소 설정 모델링에 관한 연구)

  • Noh, HyunSeok;Woo, InSung;Hwang, MyungHwan;Woo, JungHwan
    • Journal of the Korean Institute of Gas
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    • v.22 no.1
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    • pp.78-85
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    • 2018
  • In this study, we analyzed risks of the fabrication process equipment and cleanroom for semiconductor/flat panel display (FPD) manufacturing facilities and studied the fundamental safety measures for the risk factors. We examined the explosion proof design models considering the specificity of equipment and environment, and planned to utilize the findings to provide technical standards and grounds for designing and manufacturing related equipment. We believe that this study will contribute to the establishment of technical standards for semiconductor/FPD industry and businesses in many different ways by providing optimized modeling of high-risk explosion site detection, developing safety standards and hazard countermeasures and voluntary activation of safety certification system for operation of fabrication process equipment.

An Algorithm Study to Detect Mass Flow Controller Error in Plasma Deposition Equipment Using Artificial Immune System (인공면역체계를 이용한 플라즈마 증착 장비의 유량조절기 오류 검출 실험 연구)

  • You, Young Min;Jeong, Ji Yoon;Ch, Na Hyeon;Park, So Eun;Hong, Sang Jeen
    • Journal of the Semiconductor & Display Technology
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    • v.20 no.4
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    • pp.161-166
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    • 2021
  • Errors in the semiconductor process are generated by a change in the state of the equipment, and errors usually arise when the state of the equipment changes or when parts that make up the equipment have flaws. In this investigation, we anticipated that aging of the mass flow controller in the plasma enhanced chemical vapor deposition SiO2 thin film deposition method caused a minute flow rate shift. In seven cases, fourier transformation infrared film quality analysis of the deposited thin film was used to characterize normal and pathological processes. The plasma condition was monitored using optical emission spectrometry data as the flow rate changed during the procedure. Preprocessing was used to apply the collected OES data to the artificial immune system algorithm, which was then used to process diagnosis. Through comparisons between datasets, the learning algorithm compared classification accuracy and improved the method. It has been confirmed that data characterized as a normal process and abnormal processes with differing flow rates may be discriminated by themselves using the artificial immune system data mining method.

A Study on the Structural Dynamic Design for Sub-micro Vibration Control in High Class Semiconductor Factor by Semi-Empirical Method (준 경험기법을 이용한 고집적 반도체공장의 미진동 제어를 위한 구조물의 동적설계에 관한 연구)

  • 이홍기;백재호;원영재;박해동;김두훈
    • Journal of KSNVE
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    • v.9 no.6
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    • pp.1227-1233
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    • 1999
  • Modern technology depends on the reliability of extremely high technology equipments. In the production of semiconductor wafer, optical and electron microscopes, ion-beam, laser device must maintain their alignments within a nanometer. This equipment requires a vibration free environment to provide its proper function. Especially, lithography and inspection devices, which have sub-nanometer class high accuracy and resolution, have come to necessity for producing more improved giga and tera class semiconductor wafers. This high technology equipments require very strict environmental vibration standard, vibration criteria, in proportion to the accuracy of the manufacturing, inspecting devices. This paper deals with the structural dynamic design in high class semiconductor factory in order to be satisfied more strict vibration criteria for high sensitive equipment.

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A Study on Cleaning Processes for Ti/TiN Scales on Semiconductor Equipment Parts (반도체 장비 부품의 Ti/TiN 흡착물 세정 공정 연구)

  • 유정주;배규식
    • Journal of the Semiconductor & Display Technology
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    • v.3 no.2
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    • pp.11-15
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    • 2004
  • Scales, accumulated on some parts of semiconductor equipments such as sputters and CVD during the device fabrication processes, often lower the lifetime of the equipments and production yields. Thus, many equipment parts have be cleaned regularly. In this study, an attempt to establish an effective process to remove scales on the sidewall of collimators located inside the chamber of the sputter was made. The EDX analysis revealed that the scales were composed of Ti and TiN with the columnar structure. Through the trial-and-error experiments, it was found that the etching in the $HNO_3$:$H_2SO_4$:$H_2O$=4:2:4 solution for 5.5 hrs at $67^{\circ}C$, after the oxide removal in the HF solution, and the heat-treatment at $700^{\circ}C$ for 1 min., was the most effective process for the scale removal.

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Analysis of Equipment Factor for Smart Manufacturing System (스마트제조시스템의 설비인자 분석)

  • Ahn, Jae Joon;Sim, Hyun Sik
    • Journal of the Semiconductor & Display Technology
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    • v.21 no.4
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    • pp.168-173
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    • 2022
  • As the function of a product is advanced and the process is refined, the yield in the fine manufacturing process becomes an important variable that determines the cost and quality of the product. Since a fine manufacturing process generally produces a product through many steps, it is difficult to find which process or equipment has a defect, and thus it is practically difficult to ensure a high yield. This paper presents the system architecture of how to build a smart manufacturing system to analyze the big data of the manufacturing plant, and the equipment factor analysis methodology to increase the yield of products in the smart manufacturing system. In order to improve the yield of the product, it is necessary to analyze the defect factor that causes the low yield among the numerous factors of the equipment, and find and manage the equipment factor that affects the defect factor. This study analyzed the key factors of abnormal equipment that affect the yield of products in the manufacturing process using the data mining technique. Eventually, a methodology for finding key factors of abnormal equipment that directly affect the yield of products in smart manufacturing systems is presented. The methodology presented in this study was applied to the actual manufacturing plant to confirm the effect of key factors of important facilities on yield.

A Dual-Level Knowledge-Based Synthesis System for Semiconductor Chip Encapsulation

  • Yong Jeong, Heo
    • Proceedings of the Korean Society Of Semiconductor Equipment Technology
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    • 2003.12a
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    • pp.154-159
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    • 2003
  • Semiconductor chip encapsulation process is employed to protect the chip and to achieve optimal performance of the chip. Expert decision-making to obtain the appropriate package design or process conditions with high yields and high productivity is quite difficult. In this paper, an expert system for semiconductor chip encapsulation has been constructed which combines a knowledge-based system with CAE software.

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