• ETRI Journal
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• v.7 no.4
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• pp.11-14
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• 1985

A polysilicon self-aligned bipolar n-p-n transistor structure is described, which can be used in high speed and high packing density LSI circuits The emitter of this transistor is separated less than $0.4\mum$ with base contact by polysilicon self-align technology. Through all the process, the active region of this device is not damaged. therefore a high performance device is obtained. Using the transistor with $3.0\mum$ design rules, a CML ring oscillator has per-gate minimum propagation delay time of 400 ps at 2.7 mW power consumption condition.

• Journal of the Korean Vacuum Society
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• v.8 no.4B
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• pp.536-540
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• 1999

We have developed a refractory WNx self-aligned gate GaAs metal-semiconductor field-effect transistor(MESFET) using $SiO_2$ side-wall process. The MESFET hasa fully ion-implanted, planar, symmetric self-alignment structure, and it is quite suitable for integration. The uniform trans-conductance of 354nS/mm up to Vgs=+0.6V and the saturation current of 171mA/mm were obtained. As high as 43GHz of cut-off frequency hs been realized without any de-embedding of parasitic effects. The refractory WNx self-aligned gate GaAs MESFET technology is one of the most promising candidates for realizing linear power amplifier ICs and multifunction monolithic ICs for use in the digital mobile communication systems such as hand-held phone(HHP), personal communication system (PCS) and wireless local loop(WLL).

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.3
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• pp.167-172
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• 1999

The device characteristics of the base resistance controlled thyristor with self-align corrugated p-base is demonstrated for the first time with varying the n+ cathode width and the temperature form room temperature to $125^{\circ}C$. The experimental results show that the snap-back in the CB-BRT is significantly suppressed irrespective of the various n+ cathode width and the temperature as compared with that of the conventional BRT. The maximum controllable current of the CB-BRT is uniformly higher when compared with that of the conventional BRT over the temperature range from room temperature to $125^{\circ}C$.

• Journal of the Korean Society for Precision Engineering
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• v.21 no.7
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• pp.124-129
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• 2004

Recently, the demand for the optical cable is rapidly growing because the number of internee user increases and high speed internet data transmission is required. But the present optical cable winding systems has some serious problems such as pile-up and collapse of cable usually near the flange of the bobbin in the process of the cable winding. To reduce the pile-up collapse in a cable winding systems, a new guiding system is developed for a high-speed self-align cable winding. First of all, the winding mechanism was analyzed and synchronization logics for the motions of winding, traversing, and the guiding were created. A prototype cable winding systems was manufactured to validate the new guiding system and the suggested logic. Experiment results showed that the winding system with the developed guiding system outperformed the system without the guiding system in reducing pile-up and collapse in the high-speed winding.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.59 no.4
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• pp.450-455
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• 2010

The performance modeling of a $25{\mu}m$ pitch VGA ${\mu}$-bolometer with the self-aligned thermal resistor structure is carried out. The self-aligned thermal resistor can be utilized for the maximizing the thermal resistance and the fill factor of a bolometer, so the performance improvement can be expected. From the results of the performance modeling of the micro-bolometer with self-align thermal resistor for a $25{\mu}m$ pitch $640{\times}480$ microbolometer designed with $0.6{\mu}m$ minimum feature size, the drastic improvements of NETD from 38.7 mK to 19.1 mK, responsivity of 1.9 times are expected with a self aligned thermal resistor structure. The main reason for the performance improvements with a self-aligned thermal resistor structure comes from the increasement of the thermal resistance.

• Proceedings of the Korean Vacuum Society Conference
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• 1999.07a
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• pp.162-162
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• 1999

초고주파 집적회로의 핵심소자로 각광을 받고 있는 GaAs MESFET(MEtal-emiconductor)은 게이트 형성 공정이 가장 중요하며, WNx 내화금속을 이용한 planar 게이트 구조의 경우 임계전압(Vth:threshold voltage)의 균일도가 우수할 뿐만 아니라 특히 Side-wall을 이용한 self-align 게이트는 소오스 저항을 줄일 수 있어 고성능의 소자 제작을 가능하게 한다.(1) 본 연구의 핵심이 되는 Side-wall을 형성하기 위하여 PECVD법에 의한 SiOx 박막을 증착하고, 건식식각법을 이용하여 SiOx side-wall을 형성하였다. 이 공정을 이용하여 소오스 저항이 낮고 임계전압의 균일도가 우수한 고성능의 self-aligned gate MESFET을 제작하였다. 3inch GaAs 기판상에 이온주입법에 의한 채널 형성, d.c. 스퍼터링법에 의한 WNx 증착, PECVD법에 의한 SiOx 증착, MERIE(Magnetic Enhanced Reactive Ion Etcing)에 의한 Side-wall 형성, LDD(Lightly Doped Drain)와 N+ 이온주입, 그리고 RTA(Rapid Thermal Annealing)를 사용하여 활성화 공정을 수행하였다. 채널은 40keV, 4312/cm2로, LDD는 50keV, 8e12/cm2로 이온주입하였고, 4000A의 SiOx를 증착한 후 2500A의 Side-wall을 형성하였다. 옴익 접촉은 AuGe/Ni/Au 합금을 이용하였고, 소자의 최종 Passivation은 SiNx 박막을 이용하였다. 제작된 소자의 전기적 특성은 hp4145B parameter analyzer를 이용한 전압-전류 측정을 통하여 평가하였다. Side-wall 형성은 0.3$\mu\textrm{m}$ 이상의 패턴크기에서 수직으로 잘 형성되었고, 본 연궁에서는 게이트 길이가 0.5$\mu\textrm{m}$인 MESFET을 제작하였다. d.c. 특성 측정 결과 Vds=2.0V에서 임계전압은 -0.78V, 트랜스컨덕턴스는 354mS/mm, 그리고 포화전류는 171mA/mm로 평가되었다. 특히 본 연구에서 개발된 트랜지스터의 게이트 전압 변화에 따른 균일한 트랜스 컨덕턴스의 특성은 RF 소자로 사용할 때 마이크로 웨이브의 왜곡특성을 없애주기 때문에 균일한 신호의 전달을 가능하게 한다. 0.5$\mu\textrm{m}$$\times$100$\mu\textrm{m}$ 게이트 MESFET을 이용한 S-parameter 측정과 Curve fitting 으로부터 차단주파수 fT는 40GHz 이상으로 평가되었고, 특히 균일한 트랜스컨덕턴스의 경향과 함께 차단주파수 역시 게이트 바이어스, 즉 소오스-드레스인 전류의 변화에 따라 균일한 값을 보였다. 본 연구에서 개발된 Side-wall 공정은 게이트 길이가 0.3$\mu\textrm{m}$까지 작은 경우에도 사용가능하며, WNx self-align gate MEESFET은 낮은 소오스저항, 균일한 임계전압 특성, 그리고 높고 균일한 트랜스 컨덕턴스 특성으로 HHP(Hend-Held Phone) 및 PCS(Personal communication System)와 같은 이동 통신용 단말기의 MMICs(Monolithic Microwave Integrates Circuits)의 제작에 활용될 것으로 기대된다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.10
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• pp.853-858
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• 2003

In this study, a new simplified technology for fabricating high density trench gate DMOSFETs using only three mask layers and TEOS/nitride spacer is proposed. Due to the reduced masking steps and self-aligned process, this technique can afford to fabricate DMOSFETs with high cell density up to 100 Mcell/inch$^2$ and cost-effective production. The resulting unit cell pitch was 2.3∼2.4${\mu}$m. The fabricated device exhibited a excellent specific on-resistance characteristic of 0.36m$\Omega$. cm$^2$ with a breakdown voltage of 42V. Moreover, time to breakdown of gate oxide was remarkably increased by the hydrogen annealing after trench etching.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.45 no.2
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• pp.249-255
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• 1996

A self-aligned latch-up suppressed IGBT has been proposed and the process method and the device characteristics of the IGBT have been verified by numerical simulation. As the source is laterally diffused through the sidewall of the trench in the middle of the body, the size of the source is small and the doping concentration of the source is lower than that of the p++ body and the emitter efficiency of the parasitic npn transistor is low so that latch-up may be suppressed. No additional mask steps for p++ region, source, and source contact are required so that small sized body can be obtained Latch-u current density higher than 10000 A/cm$^{2}$ have been achieved by adjusting the process conditions.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2002.05a
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• pp.478-482
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• 2002

Recently, the demand for the optical cable is rapidly glowing because the number of internet user increases and high speed internet data transmission is required. To meet this demand, it is necessary to have a sufficient manufacturing capability for mass and high-quality production. But the present optical cable winding system has some serious problems such that the optical cable of radius (6 mm -40 mm) is often piled up and collapsed usually at the edge of the bobbin in the process of the cable winding. It is often necessary to have an additional operator in order to adjust the cable, which causes the productivity decrease. In order to improve a performance of cable winding system which deals with relatively thick cable( radius : 6 mm -40 mm ), we developed a new guiding system for a high-speed self-align cable winding. First of all, the winding mechanism was analyzed. Synchronization logics for the motions of winding, traversing, and the guiding were created and implemented by using the PLC and guiding system controller in a prototype cable winding system manufactured in the CILS( Computer Integrated Large scale System ) lab. An experimental verification was carried out to validate the logic. Results showed that the winding system with the developed guiding system outperformed in reducing pile-up and collapse in the high-speed winding(up to 300 mm/s) compared with the system without the guiding system.

• Journal of Advanced Navigation Technology
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• v.18 no.4
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• pp.364-370
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• 2014

In this paper, high reliable trench formation technique and a novel fabrication techniques for trench gate MOSFET is proposed which is a key to expend application of power MOSFET in the future. Trench structure has been employed device to improve Ron characteristics by shrinkage cell pitch size in DMOSFET and to isolate power device part from another CMOS device part in some power integrated circuit. A new process method for fabricating very high density trench MOSFETs using mask layers with oxide spacers and self-align technique is realized. This technique reduces the process steps, trench width and source and p=body region with a resulting increase in cell density and current driving capability and decrease in on resistance.