Journal of Advanced Navigation Technology (한국항행학회논문지)

The Korean Navigation Institute (한국항행학회)
권호 표지
DOI QR코드

DOI QR Code

A New Manufacturing Technology and Characteristics of Trench Gate MOSFET

새로운 트렌치 게이트 MOSFET 제조 공정기술 및 특성

  • Baek, Jong-Mu (Department of Electronic Communication Engineering, Daewon University College) ;
  • Cho, Moon-Taek (Department of Electrical & Electronic Engineering, Daewon University College) ;
  • Na, Seung-Kwon (Department of Biomedical Engineering, Korea Polytechnic College Wonju Campus)
  • 백종무 (대원대학교 전자정보통신과) ;
  • 조문택 (대원대학교 전기전자계열) ;
  • 나승권 (한국폴리텍대학 원주캠퍼스 의용공학과)
  • Received : 2014.07.11
  • Accepted : 2014.08.20
  • Published : 2014.08.30
Download PDF
⟨ Previous Next ⟩

Abstract

In this paper, high reliable trench formation technique and a novel fabrication techniques for trench gate MOSFET is proposed which is a key to expend application of power MOSFET in the future. Trench structure has been employed device to improve Ron characteristics by shrinkage cell pitch size in DMOSFET and to isolate power device part from another CMOS device part in some power integrated circuit. A new process method for fabricating very high density trench MOSFETs using mask layers with oxide spacers and self-align technique is realized. This technique reduces the process steps, trench width and source and p=body region with a resulting increase in cell density and current driving capability and decrease in on resistance.

본 논문에서는 트렌치 게이트 MOSFET에 적용을 위한 고 신뢰성을 갖는 트렌치 형성기술과 고품격의 제조기술을 제안하였다. 이는 향후 전력용 MOSFET 에 널리 적용이 가능하다. 트렌치 구조는 DMOSFET에서 셀 피치크기를 줄여서 Ron 특성을 개선하거나 대다수 전력용 IC에서 전력용 소자를 다른 CMOS(Complementary Metal Oxide Semiconductor) 소자로부터 독립시킬 목적으로 채용된다. 마스크 레이어를 사용하여 자기정렬기술과 산화막 스페이서가 채용된 고밀도 트렌치 MOSFET를 제작하기 위한 새로운 공정방법을 구현하였다. 이 기술은 공정 스텝수를 감소시키고 트렌치 폭과 소오스, p-body 영역을 감소시킴으로써 결과적으로 셀 밀도와 전류 구동성능을 증가시키며 온 저항의 감소를 가져왔다.

Keywords

References

  1. B. J. Baliga, Power semiconductor Devices, Boston, MA: PWS Publishing Company, 2012.
  2. K. Shenai, P. A .Piacente, R. Saia, W. Hennessy, C. C. Korman, and B. J. Baliga, "A novel high-frequency power FET structure fabricated using LPCVD WSi2 gate and LPCVD W source contact technology," IEDM Technical Digest, pp. 804-808, Dec., 1985.
  3. D. Ueda, H, Takagi and G. Kano, "An ultra-low on resistance power MOSFET fabricated by using a fully self aligned process," IEEE Transactions on Electronic Devices, Vol. ED-34, No. 4, pp. 926-930, Apr., 1987.
  4. M. Sato and Y. Arita, "Etched Shape Control of Single-Crystal Silicon in Reactive Ion Etching Using Chlorine," Journal of The Electrochemical Society, Vol. 134, pp. 2856, 1987. https://doi.org/10.1149/1.2100301
  5. S. Chae, K. Park, S. Han, J. Ha and J. Park, "Plasma induced charging damage on thin gate oxide," IEEE Transactions on. Electronic Devices, Vol. ST-P19, pp. 497-500, Feb., 1999.
  6. F.Fong, D. Pitzer and R. J.Zeman, "Power DMOS for high frequency and switching application", IEEE Transactions on. Electronic Devices, Vol. ED-27, No. 2, pp.322-330, Feb., 1980.
  7. G. Chen, S. Sapp, N.Wylie and C. Hu, "A novel contact process for power MOSFET's," IEEE Electronic Devices Letters, Vol. EDL-7, No.12, pp.672-673, Dec., 1986.
  8. B. J. Baliga, "A power junction gate field-effect transistor structure with high blocking gain," IEEE Transactions on. Electronic Devices, Vol. ED-27, pp.368-373, Feb. 1980.
  9. J. D. Mein, et al.,"A high voltage MOS switch," IEEE F. Solid-State Circuits, Vol. SC-10, pp.136-146, June 1975.
  10. S. Chae, K. Park, S. Han, J. Ha and J. Park,"Plasma induced charging damage on thin gate oxide," IEEE Transactions on Electronic Devices, Vol. ST-P19, pp. 497-500, Feb. 1999.