• 제목/요약/키워드: reduced bias

검색결과 284건 처리시간 0.027초

Self Calibration Current Bias 회로에 의한 10-bit 100 MSPS CMOS D/A 변환기의 설계 (A 10-bit 100 MSPS CMOS D/A Converter with a Self Calibration Current Bias Circuit)

  • 이한수;송원철;송민규
    • 대한전자공학회논문지SD
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    • 제40권11호
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    • pp.83-94
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    • 2003
  • 본 논문에서는 빠른 정착시간을 갖는 전류셀(Current Cell) 매트릭스의 구조와 출력의 Gain error를 보정할 수 있는 Self calibration current bias 회로의 기능을 가진 고성능 10-bit D/A 변환기를 제안한다. 매트릭스 구조 회로의 복잡성으로 인한 지연시간의 증가 및 전력 소모를 최소화하기 위해 상위 6MSB(Most Significant Bit)전류원 매트릭스와 하위 4LSB(Least Significant Bit)전류원 매트릭스로 구성된 2단 매트릭스 구조로 설계되어 있다. 이러한 6+4 분할 구조를 사용함으로써 전류 원이 차지하는 면적과 Thermometer decoder 부분의 논리회로를 가장 최적화 시켜 회로의 복잡성과 Chip 사이즈를 줄일 수 있었고 낮은 Glitch 특성을 갖는 저 전력 D/A 변환기를 구현하였다. 또한 self Calibration이 가능한 Current Bias를 설계함으로서 이전 D/A 변환기들의 칩 외부에 구현하던 Termination 저항을 칩 내부에 구현하고 출력의 선형성 및 정확성을 배가시켰다. 본 연구에서는 3.3V의 공급전압을 가지는 0.35㎛ 2-poly 4-metal N-well CMOS 공정을 사용하였고, 모의 실험결과에서 선형성이 매우 우수한 출력을 확인하였다. 또한 소비전력은 45m W로 다른 10bit D/A 변환기에 비해 매우 낮음을 확인 할 수 있었다. 실제 제작된 칩은 Spectrum analyzer에 의한 측정결과에서 100㎒ 샘플링 클럭 주파수와 10㎒ 입력 신호 주파수에서 SFDR은 약 65㏈로 측정되었고, INL과 DNL은 각각 0.5 LSB 이하로 나타났다. 유효 칩 면적은 Power Guard ring을 포함하여 1350㎛ × 750 ㎛ 의 면적을 갖는다.

Efficacy of ketamine in the treatment of migraines and other unspecified primary headache disorders compared to placebo and other interventions: a systematic review

  • Chah, Neysan;Jones, Mike;Milord, Steve;Al-Eryani, Kamal;Enciso, Reyes
    • Journal of Dental Anesthesia and Pain Medicine
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    • 제21권5호
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    • pp.413-429
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    • 2021
  • Background: Migraine headaches are the second leading cause of disability worldwide and are responsible for significant morbidity, reduction in the quality of life, and loss of productivity on a global scale. The purpose of this systematic review and meta-analysis was to evaluate the efficacy of ketamine on migraines and other primary headache disorders compared to placebo and other active interventions, such as midazolam, metoclopramide/diphenhydramine, and prochlorperazine/diphenhydramine. Methods: An electronic search of databases published up to February 2021, including Medline via PubMed, EMBASE, Web of Science, and Cochrane Library, a hand search of the bibliographies of the included studies, as well as literature and systematic reviews found through the search was conducted to identify randomized controlled trials (RCTs) investigating ketamine in the treatment of migraine/headache disorders compared to the placebo. The authors assessed the risk of bias according to the Cochrane Handbook guidelines. Results: The initial search strategy yielded 398 unduplicated references, which were independently assessed by three review authors. After evaluation, this number was reduced to five RCTs (two unclear risk of bias and three high risk of bias). The total number of patients in all the studies was 193. Due to the high risk of bias, small sample size, heterogeneity of the outcomes reported, and heterogeneity of the comparison groups, the quality of the evidence was very low. One RCT reported that intranasal ketamine was superior to intranasal midazolam in improving the aura attack severity, but not duration, while another reported that intranasal ketamine was not superior to metoclopramide and diphenhydramine in reducing the headache severity. In one trial, subcutaneous ketamine was superior to saline in migraine severity reduction; however, intravenous (I.V.) ketamine was inferior to I.V. prochlorperazine and diphenhydramine in another study. Conclusion: Further double-blind controlled studies are needed to assess the efficacy of ketamine in treating acute and chronic refractory migraines and other primary headaches using intranasal and subcutaneous routes. These studies should include a long-term follow-up and different ketamine dosages in diagnosed patients following international standards for diagnosing headache/migraine.

70-nm 이하 급 초미세 CMOS 공정에서의 누설 전류 및 동적 전류 소비 억제 내장형 SRAM 설계 (Leakage-Suppressed SRAM with Dynamic Power Saving Scheme for Future Sub-70-nm CMOS Technology)

  • 최훈대;최현영;김동명;김대정;민경식
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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    • pp.343-346
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    • 2004
  • This paper proposes a leakage-suppressed SRAM with dynamic power saying scheme for the future leakage-dominant sub-70-nm technology. By dynamically controlling the common source-line voltage ($V_{SL}$) of sleep cells, the sub-threshold leakage through these sleep cells can be reduced to be 1/10-1/100 due to the reverse body-bias effect, dram-induced barrier lowering (DIBL) and negative $V_{GS}$ effects. Moreover, the bit-ling leakage which mar introduce a fault during the read operation can be completely eliminated in this new SRAM. The dynamic $V_{SL}$ control can also reduce the bit-line swing during the write so that the dynamic power in write can be reduced. This new SRAM was fabricated in 0.35-${\mu}m$ CMOS process and more than $30\%$ of dynamic power saying is experimentally verified in the measurement. The leakage suppression scheme is expected to be able to reduce more than $90\%$ of total SRAM power in the future leakage-dominant 70-nm process.

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CMOS Binary Image Sensor with Gate/Body-Tied PMOSFET-Type Photodetector for Low-Power and Low-Noise Operation

  • Lee, Junwoo;Choi, Byoung-Soo;Seong, Donghyun;Lee, Jewon;Kim, Sang-Hwan;Lee, Jimin;Shin, Jang-Kyoo;Choi, Pyung
    • 센서학회지
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    • 제27권6호
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    • pp.362-367
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    • 2018
  • A complementary metal oxide semiconductor (CMOS) binary image sensor is proposed for low-power and low-noise operation. The proposed binary image sensor has the advantages of reduced power consumption and fixed pattern noise (FPN). A gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector is used as the proposed CMOS binary image sensor. The GBT PMOSFET-type photodetector has a floating gate that amplifies the photocurrent generated by incident light. Therefore, the sensitivity of the GBT PMOSFET-type photodetector is higher than that of other photodetectors. The proposed CMOS binary image sensor consists of a pixel array with $394(H){\times}250(V)$ pixels, scanners, bias circuits, and column parallel readout circuits for binary image processing. The proposed CMOS binary image sensor was analyzed by simulation. Using the dynamic comparator, a power consumption reduction of approximately 99.7% was achieved, and this performance was verified by the simulation by comparing the results with those of a two-stage comparator. Also, it was confirmed using simulation that the FPN of the proposed CMOS binary image sensor was successfully reduced by use of the double sampling process.

Suppression of Gate Oxide Degradation for MOS Devices Using Deuterium Ion Implantation Method

  • Lee, Jae-Sung
    • Transactions on Electrical and Electronic Materials
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    • 제13권4호
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    • pp.188-191
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    • 2012
  • This paper introduces a new method regarding deuterium incorporation in the gate dielectric including deuterium implantation and post-annealing at the back-end-of-the process line. The control device and the deuterium furnace-annealed device were also prepared for comparison with the implanted device. It was observed that deuterium implantation at a light dose of $1{\times}10^{12}-1{\times}10^{14}/cm^2$ at 30 keV reduced hot-carrier injection (HCI) degradation and negative bias temperature instability (NBTI) within our device structure due to the reduction in oxide charge and interface trap. Deuterium implantation provides a possible solution to enhance the bulk and interface reliabilities of the gate oxide under the electrical stress.

A Study on the Detection Algorithm of an Advanced Ultrasonic Signal for Hydro-acoustic Releaser

  • Kim, Young-Jin;Huh, Kyung-Moo;Cho, Young-June
    • International Journal of Control, Automation, and Systems
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    • 제6권5호
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    • pp.767-775
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    • 2008
  • Methods used for exploring marine resources and spaces include positioning a probe under water and then recalling it after a specified time. Hydro-acoustic Releasers are commonly used for positioning and retrieving of such exploration equipment. The most important factor in this kind of system is the reliability for recalling the instruments. The frequently used ultrasonic signal detection method can detect ultrasonic signals using a fixed comparator, but because of increased rates of errors due to outside interferences, information is repetitively acquired. This study presents an effective ultrasonic signal detection algorithm using the characteristics of a resonance and adaptive comparator Combined with the FSK+ASK modulator. As a result, approximately 8.8% of ultrasonic wave communication errors caused by background noise and transmission losses were reduced for effectively detecting ultrasonic waves. Furthermore, the resonance circuit's quality factor was enhanced (Q = 120 to 160). As such, the bias voltage of the transistor (Vb= 3.3 to 6.8V) was increased thereby enhancing the frequency's selectivity.

MR 방법으로부터 다단 정현파의 주파수 추정 (Frequency Estimation of Multiple Sinusoids From MR Method)

  • 안태천;탁현수;이종범
    • 전자공학회논문지B
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    • 제29B권2호
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    • pp.18-26
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    • 1992
  • MR(Model Reduction) is presented in order to estimate the frequency of multiple sinusoids from the finite noisy data with the white or colored noises. MR, using the reduced rank models, is designed, appling the approximation of linear system to LP(Linear Prediction). The MR method is analyzed. Monte-carlo simulations are conducted for MR and Lp. The results are compared with in terms of mean, root-mean square and relative bias. MR eliminates effectevely the extremeous and exceptional poles appearing in LP and improves the accuracy of LP. Especially, MR gives promising results in short noisy measurements, low SNR's and colored noises. Power spectral density and angular frequency position are showed by figures, for examples. Finally, the new method is utilized to the communication and biomedical systems estimating the characteristics of the signal and the system identification modelling the dynamic systems from experimental data.

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On Line LS-SVM for Classification

  • Kim, Daehak;Oh, KwangSik;Shim, Jooyong
    • Communications for Statistical Applications and Methods
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    • 제10권2호
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    • pp.595-601
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    • 2003
  • In this paper we propose an on line training method for classification based on least squares support vector machine. Proposed method enables the computation cost to be reduced and the training to be peformed incrementally, With the incremental formulation of an inverse matrix in optimization problem, current information and new input data can be used for building the new inverse matrix for the estimation of the optimal bias and Lagrange multipliers, so the large scale matrix inversion operation can be avoided. Numerical examples are included which indicate the performance of proposed algorithm.

디스크 표면 토포그래피가 자기저항 헤드의 베이스라인 안정성에 미치는 영향 (The Effects of Disk Surface Topography on Baseline Instability of MR Head)

  • 좌성훈
    • 대한기계학회논문집A
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    • 제24권2호
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    • pp.311-318
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    • 2000
  • Several factors which influence baseline instability (BLI) phenomenon in MR drive were investigated experimentally. In particular, the role of surface topography on BLI was studied in detail. The r esults show that BLI is linearly proportional to the surface waviness with a spatial wavelength of 0.4 to 5.0 min. BLI becomes worse as the surface waviness increases. On the other hand, surface roughness which has a spatial wavelength below 25 $\mu$ m has no effect on BLI. The results further show that the effect of bias current on the BLI is amplified on the disk with worse surface waviness. The disk surface waviness is dependent on the manufacturing process and becomes an inherent surface property of media. The disk surface waviness. therefore, can not be overlooked when evaluating the media for a high-performance hard disk drive. In general, waviness is reduced mainly during grinding and polishing process during manufacturing.

초격자 Buffer를 사용한 InGaN/GaN 양자우물에서 Piezoelectric 효과의 측정과 Strain 감소에 대한 연구 (Measurement of Piezoelectric Effect and Reduction of Strain in InGaN/GaN Quantum Well with Superlattice Buffer)

  • 공경식;안주인;이석주
    • 한국전기전자재료학회논문지
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    • 제21권6호
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    • pp.503-508
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    • 2008
  • In order to reduce the piezoelectric field originated from the well layer which resides in InGaN/GaN light emitting diode, InGaN/GaN superlattice buffer layers were grown at the bottom and the top of the active layer. Measuring the photoluminescence spectra with different reverse bias voltages clearly revealed the condition of the flat band under which the transition energy is maximized and the linewidth is minimized. Accordingly, the piezoelectric field of $In_{0.15}Ga_{0.85}N$ in our sample was estimated as -1.08 MV/cm. It is less than half the value reported in the previous studies, and it is evidenced that the strain has reduced due to the superlattice buffer layers.