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Suppression of Gate Oxide Degradation for MOS Devices Using Deuterium Ion Implantation Method

  • Lee, Jae-Sung (Department of Information and Communication Engineering, Uiduk University)
  • Received : 2012.05.07
  • Accepted : 2012.06.12
  • Published : 2012.08.25

Abstract

This paper introduces a new method regarding deuterium incorporation in the gate dielectric including deuterium implantation and post-annealing at the back-end-of-the process line. The control device and the deuterium furnace-annealed device were also prepared for comparison with the implanted device. It was observed that deuterium implantation at a light dose of $1{\times}10^{12}-1{\times}10^{14}/cm^2$ at 30 keV reduced hot-carrier injection (HCI) degradation and negative bias temperature instability (NBTI) within our device structure due to the reduction in oxide charge and interface trap. Deuterium implantation provides a possible solution to enhance the bulk and interface reliabilities of the gate oxide under the electrical stress.

Keywords

References

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