• Title/Summary/Keyword: queueing performance

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Design and Analsis of a high speed switching system with two priority (두개의 우선 순위를 가지는 고속 스윗칭 시스템의 설계 및 성능 분석)

  • Hong, Yo-Hun;Choe, Jin-Sik;Jeon, Mun-Seok
    • The KIPS Transactions:PartC
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    • v.8C no.6
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    • pp.793-805
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    • 2001
  • In the recent priority system, high-priority packet will be served first and low-priority packet will be served when there isn\`t any high-priority packet in the system. By the way, even high-priority packet can be blocked by HOL (Head of Line) contention in the input queueing System. Therefore, the whole switching performance can be improved by serving low-priority packet even though high-priority packet is blocked. In this paper, we study the performance of preemptive priority in an input queueing switch for high speed switch system. The analysis of this switching system is taken into account of the influence of priority scheduling and the window scheme for head-of-line contention. We derive queue length distribution, delay and maximum throughput for the switching system based on these control schemes. Because of the service dependencies between inputs, an exact analysis of this switching system is intractable. Consequently, we provide an approximate analysis based on some independence assumption and the flow conservation rule. We use an equivalent queueing system to estimate the service capability seen by each input. In case of the preemptive priority policy without considering a window scheme, we extend the approximation technique used by Chen and Guerin [1] to obtain more accurate results. Moreover, we also propose newly a window scheme that is appropriate for the preemptive priority switching system in view of implementation and operation. It can improve the total system throughput and delay performance of low priority packets. We also analyze this window scheme using an equivalent queueing system and compare the performance results with that without the window scheme. Numerical results are compared with simulations.

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Method for Reduction of Power Consumption using Buffer Processing Time Control in Home Gateway (홈 게이트웨이에서 서비스 특성에 따른 버퍼 동작 시간 제어를 통한 전력 소비 감소 방안)

  • Yang, Hyeon;Yu, Gil-Sang;Kim, Yong-Woon;Choi, Seong-Gon
    • The Journal of the Korea Contents Association
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    • v.12 no.8
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    • pp.69-76
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    • 2012
  • This paper proposes an efficient power consumption scheme using sleep mode in home gateway. The scheme by this paper classifies incoming real time packet and non-real time packet in home gateway and delay non-real time packet. Therefore, the home gateway can have longer sleep time because non-real time packet can get additional delay time by proposing mechanism using timer. We use non-preemptive two priority queueing model for performance analysis. As a results, we verify that power consumption of proposed scheme is reduced more than existing scheme by delay of non-real time traffic.

Providing Guaranteed Delay in Multimedia Ad Hoc Wireless Networks (멀티미디어 Ad Hoc 무선망에서의 지연시간 보장방안)

  • Yang, Hyun-ho
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.7 no.6
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    • pp.1177-1186
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    • 2003
  • The multimedia ad hoc wireless network is quite an attractive issue since it offers a flexible solution to enable delivery of multimedia services to mobile end users without fixed backbone networks. However, with the unique design challenges of ad hoc wireless networks, it is a non-trivial issue to provide bounded delay guarantee, with fair share of resources. In this paper, we implemented the delay guaranteed fair queueing (DGFQ) scheme distributively. Through the results of performance evaluation, we can conclude that DGFQ also performs well to control bounded delay in multimedia ad hoc wireless networks.

Analysis of Finite Tandem Queues in Computer Communication Network (컴퓨터 통신망의 유한 길이 탄뎀 큐에 대한 해석)

  • 조진웅;이재호
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.12 no.6
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    • pp.545-553
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    • 1987
  • An approximation algorithm has been obtained to analyze the network of single server tandem queues with a finite length. In the queueing network with a finite queue length, the blocking which is mutually dependent, occure due to the limitation of the queue length. Thus, it is difficults to analyze such a queueing network. In this paper each queue has been regarded as the independent M/M/1/K system to analyze the queueing network with the blocking, which is based on the assumption that an arrival rate to the present station is increased by the blocking of the following stations. The performance measures, such as state probability, average queue length and tha waiting time, can be easily obtained using the proposed algorithm. In order to justify this approximation algorithm, comparison of the results of this algorithm with those of state transition simultaneous equations has been made an verified with computer simulation.

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Performance study of the priority scheme in an ATM switch with input and output queues (입출력 큐를 갖는 ATM 스위치에서의 우선순위에 관한 성능 분석)

  • 이장원;최진식
    • Journal of the Korean Institute of Telematics and Electronics S
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    • v.35S no.2
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    • pp.1-9
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    • 1998
  • ATM was adopted as the switching and multiplexing technique for BISDN which aims at transmitting traffics with various characteristics in a unified network. To construct these ATM networks, the most important aspect is the design of the switching system with high performance and different service capabilities. In this paepr, we analyze the performance of an input and output queueing switch with preemptive priority which is considered to be most suitable for ATM networks. For the analysis of an input queue, we model each input queue as two separate virtual input queues for each priority class and we approximage them asindependent Geom/Geom/1 queues. And we model a virtual HOL queue which consists of HOL cells of all virtual input queues which have the same output address to obtain the mean service time at each virtual input queue. For the analysis of an output quque, we obtain approximately the arrival process into the output queue from the state of the virtual HOL queue. We use a Markov chain method to analyze these two models and obtain the maximum throughput of the switch and the mean queueing delay of cells. and analysis results are compared with simulation to verify that out model yields accurate results.

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Performance Estimation of AS/RS using M/G/1 Queueing Model with Two Queues (M/G/l 대기모델을 이용한 자동창고 시스템의 성능 평가)

  • Lee, Moon-Hwan;Lim, Si-Yeong;Hur, Sun;Lee, Young-Hae
    • Proceedings of the Korean Operations and Management Science Society Conference
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    • 2000.10a
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    • pp.59-62
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    • 2000
  • Many of the previous researchers have been studied for the performance estimation of an AS/RS with a static model or computer simulation. Especially, they assumes that the storage/retrieval (S/R) machine performs either only single command (SC) or dual command (DC) and their requests are known in advance. However, the S/R machine performs a SC or a DC. or both or becomes idle according to the operating policy and the status of system at an arbitrary point of time. In this paper, we propose a stochastic model for the performance estimation of a unit-load AS/RS by using a M/G/1 queueing model with a single-server and two queues. Expected numbers of waiting storage and retrieval commands, and the waiting time in queues for the storage and retrieval commands are found

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Performance Analysis of an ATM Multiplexer Loaded by CBR and Bursty Traffic Sources (CBR과 버스티 트래픽원이 가해진 ATM 다중화기의 성능 분석)

  • 김승환;박진수
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.19 no.4
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    • pp.633-638
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    • 1994
  • Asynchronous Transfer Model(ATM) has a fixed-length packet transport scheme. It is one of promising proposals in Broadband ISDN(B-ISDN). Since the packet length is fixed, it can be potentially to perform the various service to user. In this paper, a queueing model for an ATM Multiplexer loaded by the Continuous Bit Rate(CBR) traffic and the bursty traffic sources is analyzed. The queueing system has a finite buffer size. The cell loss probabilities with the simple and recurcive form for a performance measures of ATM multiplexer are derived, and are also evaluated through numerical examples. The results of this study may be used as guidelines in buffer design problems and performance analysis of ATM multiplexing system.

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Flow-Based WTP Scheduler for Proportional Differentiated Services in Wireless Communication Systems (무선통신 시스템에서의 비례지연서비스를 위한 플로우 기반 WTP 스케쥴러)

  • Park Hyosoon;Kwon Eunhyun;Kim Taehyoun;Lee Jaiyong
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.7B
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    • pp.433-439
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    • 2005
  • In this paper, we propose a Flow Based Waiting Time Priority (FB-WTP) scheduler that supports the proportional delay differentiated services between classes. Existing scheduling algorithms utilize the configuration of scheduler, which is operated as class unit, applied to wired network. However, FB-WTP scheduler is operated as flow unit and can take advantage of multi-flow diversity effect in time-varying channel state environment. As a result, FB-WTP improves the average queueing delay on each class as well as supporting the average queueing delay ratio between classes. It also solves the HOL packet blocking problem implicitly. Simulation results show that FB-WTP scheduler has better system queueing delay performance than Look-ahead Waiting Time Priority (LWTP) scheduler and supports the larger queueing delay ratio between classes that network operator set.

Design and Performance of Linear Clock Fair Queueing Algorithm (LCFQ ( Linear Clock Fair Queueing ) 알고리즘의 설계와 성능 분석)

  • Kim, Young-Han;Lee, Jae-Yong
    • Journal of the Korean Institute of Telematics and Electronics S
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    • v.36S no.1
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    • pp.1-8
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    • 1999
  • In order to provide appropriate Quality of Service(QoS) guarantee to each traffic flow in intergrated service networks, an efficient traffic scheduling algorithm as well as resource reservation must be adopted in host and transit routers. In this paper, a new efficient fair queueing algorithm which adopts a linearly increasing virtual time is presented. The proposed algorithm is fair and the maximum and mean delay guaranteed of each flow are less than those of the SCFQ(self clocked fair queueing) algorithm which is one of the most promising traffic scheduling algorithm, while providing low implementation complexity as the SCFQ scheme. And, it has the better isolation provided than SCFQ, which means that each flow is much less influenced by the violating traffic flows provided its allocated bandwidth gurantee. The fairness of the proposed algorithm is proved and simulation results of maximum and mean delay presented.

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Performance Analysis of Adaptive Separated-Queueing ATM Switch for multimedia Services (멀티미디어 서비스를 지원하는 적응적 분리 큐잉 ATM 스위치의 성능분석)

  • Im, Cheol-Su;Park, Byeong-Seop
    • The Transactions of the Korea Information Processing Society
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    • v.6 no.1
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    • pp.167-174
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    • 1999
  • In this paper, we propose the adaptive separated-queueing ATM switching model for the effective processing of the various types of multimedia traffic by virtue of ATM switching network with multiple outlets which is the essential part of B-ISDN. This proposed model employs the dynamically separated buffering mechanism in the processing of two classes of cell, realtime service traffic and non-realtime service traffic, at the output buffer to enhance the overall QoS(Quality of Service). The adopted ATM switch architecture has Batcher-banyan based network, but it uses different topologies and control techniques 6to resolve the cell contention. For the performance evaluation of our proposed method, we have done both analytical modeling and simulation. The both results show that our proposed queueing strategy is quite appropriate to the ATM switch with multiple outlets and can quarantee the QoS requirements of the incoming multimedia traffic.

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