• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.9-12
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• 2008

For the large-sized and post-ultra definition TFT-LCD, improved drivability is prerequisite not only for the integration of driving circuit on glass but also for the chargeability of each pixel. In order to meet required drivability, currently adopted process architecture and materials are modified for the RC delay reduction, including the drastic increase of gate bus thickness and its related solution for step coverage. We present new process architecture and material selection for the next generation TFT-LCD devices.

• Proceedings of the Korean Institute of Building Construction Conference
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• 2012.05a
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• pp.341-343
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• 2012

This study introduces a method for computation of process and operation gap in the specific construction operation(i.e., RC frame construction applying a block-grouping scheme) using CYCLONE-based simulation modeling and analysis technique. Since uncertainty of construction environment exists, a thoughtful production planning is required to effectively deal with a risk resulting in schedule delay in advance. This study presents the concepts of a time delay occurred in a process level and operation level in a operation model, and a method of measuring gap-times in each level while the simulation progresses. It helps a site manager to decide how many segmentation in a construction block is suitable for eliminating unproductive time-delays under the constrained resources (e.g., laborer, equipment). A case study presents a network model representing a three segmented RC frame work, and result obtained from the simulation experiment.

• Journal of Communications and Networks
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• v.8 no.1
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• pp.59-69
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• 2006

Bluetooth is reputed as a wireless networking technology supplying ad-hoc networks between digital devices. In particular, Bluetooth scatternet is an essential part of dynamic ad-hoc networks. Yet, there have not been sufficient researches performed on scatternet environment. This paper proposes a scatternet reformation algorithm for ad-hoc networks for instances where some nodes enter or leave the scatternet. The proposed algorithm is a general algorithm that can be applied to many types of Bluetooth scatternet regardless of the topology. The proposed algorithm is made for two reformation cases, i.e., nodes leaving and nodes entering. For the reformation when nodes leave a scatternet, the recovery node vector (RNV) algorithm is proposed. It has short reformation setup delay because the process involves a single page process (not including inquiry process). For the reformation when nodes enter a scatternet, the entry node algorithm is proposed. This is a simple and easily implementable algorithm. In this paper, real hardware experiments are carried out to evaluate the algorithm's performance where the reformation setup delay, the reformation setup probability and the data transfer rate are measured. The proposed algorithm has shown improvement in the reformation setup delay and probability.

• Korean Journal of Construction Engineering and Management
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• v.10 no.1
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• pp.36-44
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• 2009

The sum of each work duration are entire period in construction project. Each work occurs to be late, the total period of construction project will delays. Therefore, the total period of construction project will not be delayed if probability of work progress makes higher. Finding each work constraints performs constraints analysis in process of construction for checking probability of work progress. Grasp work constraints through the constraints analysis and removes. This research will show preventing delay of construction project, through work condition analysis process.

• Proceedings of the Korean Institute of Building Construction Conference
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• 2022.11a
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• pp.17-18
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• 2022

In Korea, asbestos removal has been actively carried out nationwide since 2015 when asbestos was completely banned as a first-class carcinogen. Since scattering dust generated in the process of removing asbestos causes fatal diseases such as asbestos lung disease and lung cancer, concerns are growing over the safety of construction workers and building users undergoing dismantling. For this reason, regulations on asbestos sites have been strengthened and prior studies on safety and risk assessment have been conducted, but research on actual site data collection and process planning is insufficient even though safety is reduced due to delay in site construction period. Therefore, it is necessary to analyze the work and delay factors of the asbestos dismantling process and develop an optimized process plan model for workers. This study is an initial step to develop an optimized process plan model that considers the safety and productivity of asbestos dismantling work, and aims to help establish an optimized process plan for asbestos dismantling process using website clone simulation.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.3
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• pp.44-54
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• 2000

In this paper, a design methodology for the frequency-adaptive negative-delay circuit which can be implemented in standard CMOS memory process is proposed. The proposed negative-delay circuit which is a basic type of the analog SMD (synchronous mirror delay) measures the time difference between the input clock period and the target negative delay by utilizing analog behavior and repeats it in the next coming cycle. A new technology that compensates the auxiliary delay related with the output clock in the measure stage differentiates the Proposed method from the conventional method that compensates it in the delay-model stage which comes before the measure stage. A wider negative-delay range especially prominent in the high frequency performance than that in the conventional method can be realized through the proposed technology. In order to implement the wide locking range, a new frequency detector and the method for optimizing the bias condition of the analog circuit are suggested. An application example to the clocking circuits of a DDR SDRAM is simulated and demonstrated in a 0.6 ${\mu}{\textrm}{m}$ n-well double-poly double-metal CMOS technology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.6
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• pp.51-56
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• 2010

In this paper, a novel Integer-N phase-delay locked loop(P DLL) architecture has been proposed using a voltage controlled delay line(VCDL). The P DLL can have the LF of one small capacitance instead of the conventional second or third-order LF. The size of chip is $255{\mu}m$ $\times$ $935.5{\mu}m$ including the LF. The proposed P DLL has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by HSPICE simulation.

• Journal of Korea Society of Digital Industry and Information Management
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• v.6 no.1
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• pp.83-90
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• 2010

DTNs (Delay Tolerant Networks) refer to the networks that can support data transmission in the extreme networking situations such as continuous delay and no connectivity between ends. DTMNs (Delay Tolerant Networks) are a specific range of DTNs, and its chief considerations in the process of message delivery in the routing protocol are the transmission delay, improvement of reliability, and reduction of network loading. This article proposes a new LCN (Largest Common Neighbor) routing algorism to improve Spray and Wait routing protocol that prevents the generation of unnecessary packets in a network by letting mobile nodes limit the number of copies of their messages to all nodes to L. Since higher L is distributed to nodes with directivity to the destination node and the maximum number of common neighbor nodes among the mobile nodes based on the directivity information of each node and the maximum number of common neighbor nodes, more efficient node transmission can be realized. In order to verify this proposed algorism, DTN simulator was designed by using ONE simulator. According to the result of this simulation, the suggested algorism can reduce average delay and unnecessary message generation.

• Journal of Korean Institute of Industrial Engineers
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• v.28 no.2
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• pp.139-146
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• 2002

The third generation mobile communication needs to provide multimedia service with increased data rates. Thus an efficient allocation of radio and network resources is very important. This paper models the 'burst switching' as an efficient radio resource allocation scheme and the performance is compared to the circuit and packet switching. In burst switching, radio resource is allocated to a call for the duration of data bursts rather than an entire session or a single packet as in the case of circuit and packet switching. After a stream of data burst, if a packet does not arrive during timer2 value ($\tau_{2}$), the channel of physical layer is released and the call stays in suspended state. Again if a packet does not arrive for timerl value ($\tau_{1}$) in the suspended state, the upper layer is also released. Thus the two timer values to minimize the sum of access delay and queuing delay need to be determined. In this paper, we focus on the decision of $\tau_{2}$ which minimizes the access and queueing delay with the assumption that traffic arrivals follow Poison process. The simulation, however, is performed with Pareto distribution which well describes the bursty traffic. The computational results show that the delay and the packet loss probability by the burst switching is dramatically reduced compared to the packet switching.

• Clinical and Experimental Pediatrics
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• v.49 no.10
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• pp.1019-1025
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• 2006

Motor delay, when present, is usually the first concern brought by the parents of children with developmental delay. Cerebral palsy that is the most common motor delay, is a nonspecific, descriptive term pertaining to disordered motor function that is evident in early infancy and is characterized by changes in muscle tone, muscle weakness, involuntary movements, ataxia, or a combination of these abnormalities. A wide range of causative disorders and risk factors have been identified for cerebral palsy, and broadly classified into 5 groups; perinatal brain injury, brain injury related to prematurity, developmental abnormalities, prenatal risk factors, and postnatal brain injury. Delay in attaining developmental milestones is the most distinctive presenting complaint in children with cerebral palsy. A detailed history and thorough physical and neurologic examinations are crucial in the diagnostic process. The clinician should be cautious about diagnostic pronouncement unless the findings are unequivocal. Several serial examinations and history review are necessary. All children with cerebral palsy should undergo a neuroimaging study, preferably MRI, because an abnormality is documented on head MRI(89%) and CT(77%). The high incidence rates for mental retardation, epilepsy, ophthalmologic defects, speech and language disorders and hearing impairment make it imperative that all children with cerebral palsy be screened for mental retardation, ophthalmologic and hearing impairments, and speech and language disorders; nutrition, growth, and swallowing also should be closely monitored.