• 전기학회논문지P
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• 제63권2호
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• pp.81-88
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• 2014

In this paper, an implementation of concurrent backoff delay process on a single chip with IEEE 802.15.4 hardware and 8051 processor core that can be used for analyzing the interference on IEEE 802.15.4 channels due to WiFi traffics is studied. The backoff delay process of IEEE 802.15.4 CSMA-CA algorithm is explained. The characteristics of random number generator, timer, and CCA register included in the single chip are described with their control procedure in order to implement the process. A concurrent backoff delay process to evaluate multiple IEEE 802.15.4 channels is proposed, and a method to service the associated tasks at sequentially ordered backoff delay events occurring on the channels is explained. For the implementation of the concurrent backoff delay process on a single chip IEEE 802.15.4 hardware, the elements for the single channel backoff delay process and their control procedure are used to be extended to multiple channels with little modification. The medium access delay on each channel, which is available after execution of the concurrent backoff delay process, is displayed on the LCD of an IEEE 802.15.4 channel analyzer. The experimental results show that we can easily identify the interference on IEEE 802.15.4 channels caused by WiFi traffics in comparison with the way displaying measured channel powers.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1994년도 Proceedings of the Korea Automatic Control Conference, 9th (KACC) ; Taejeon, Korea; 17-20 Oct. 1994
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• pp.140-145
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• 1994

In this paper, we consider a problem to estimate process parameters using input-output data collected from the process operating in closed-loop control system. When orders and delay-time of the process are known correctly, under some conditions of identifying experiments, it is reported that accurate identification results can be obtained by applying prediction error method. To get accurate estimates, it is necessary to know orders and delay-time of the process. It is difficult to determine them in closed-loop identification, because ill-condition for identification are easily caused by selection of unsuitable order or delay time. Furthermore, the procedures to select orders and delay-time in open-loop identification aren't always available in closed-loop identification. The purpose of this paper is to determine a delay-time under suitable assumption that order of the process are known as the first step.

• Journal of information and communication convergence engineering
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• 제8권4호
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• pp.461-465
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• 2010

This paper describes the design method of Time-to-Digital Converter(TDC) to obtain the constant delay time and good reliability. The reliability property is described with delay elements. In TDC the time signal is converted to digital value which is based on delay elements for the time interpolation. To obtain the constant delay time, the first and the last delay elements have different structure compared to the middle delay elements. In the first and the last delay elements, the driving ability could be controlled for the different delay time. The delay element can be designed by analog and digital devices. The delay time of the element using analog devices is not sensitive to process parameters than that of the element using digital devices. And the TDC circuit by the elements using analog devices shows better reliability than that by the elements using digital devices also.

• 한국정보전자통신기술학회논문지
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• 제16권2호
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• pp.69-76
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• 2023

MDCT/IMDCT 과정을 사용하는 고품질 오디오/음성 코덱은 이전 프레임 과의 중첩-합(Overlap-add) 과정을 통해 현재 프레임을 완벽 복원 가능하다. 중첩-합 과정에서 프레임 길이 만큼의 알고리즘 지연이 발생하게 된다. 본 논문에서는 알고리즘 지연을 줄이기 위해 MDCT/IMDCT에 가변적인 위상변이를 사용하여 알고리즘 지연을 줄인 MDCT/IMDCT 과정을 제안한다. 가변 지연 MDCT/IMDCT알고리즘을 ITU-T 표준 코덱 G.729.1 코덱에 적용하여 저지연 오디오/음성 코덱을 제안하였다. MDCT/IMDCT 과정에서의 알고리즘 지연은 기존 20 ms에서 1.25ms 까지 감소시킬 수 있다. 저지연 MDCT/IMDCT를 적용한 오디오/음성 코덱의 복호화된 출력신호는 객관적 음질 시험 방법인 PESQ 시험을 통해 성능 평가하였다. 전송 지연이 감소 됨에도 불구하고 기존 방법과 음질 차이가 없음을 확인할 수 있었다.

• 한국건축시공학회:학술대회논문집
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• 한국건축시공학회 2010년도 춘계 학술논문 발표대회 1부
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• pp.125-129
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• 2010

The ultimate goal of construction is to complete the given work in the most economical and safest way within the required construction period while meeting the quality standards specified in the design drawing. There are a few characteristics of finish work. First, executed in subdivided processes, finish work involves a very diverse and complex structure. Second, there are no criteria for each segmented process with regard to the appropriate time of input. Third, it is not very necessary to set priorities for lead and lag works. This study intends to provide information on the completion of a project in accordance with the required duration by setting priorities in the delay of each detailed process of finish work to minimize delay in finish work. In this study, finish work is divided into wet work and other types of finish work, and the importance of each process is classified based on the given details of each process. In addition, the study employs a survey to analyze delay factors of a designer, a constructor, and a supplier. Using the survey results, the study sets priorities in delay of final work to provide information on the completion of an apartment project within the planned construction period.

• 한국산업정보학회논문지
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• 제20권1호
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• pp.1-7
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• 2015

In this paper, a 12-bit high resolution, power and area efficiency hybrid digital pulse width modulator (DPWM) with process and temperature (PT) calibration has been proposed for digital controlled DC-DC converters. The hybrid structure of DPWM combines a 6-bit differential tapped delay line ring-mux digital-to-time converter (DTC) schema and a 6-bit counter-comparator DTC schema, resulting in a power and area saving solution. Furthermore, since the 6-bit differential delay line ring oscillator serves as the clock to the high 6-bit counter-comparator DTC, a high frequency clock is eliminated, and the power is significantly saved. In order to have a simple delay cell and flexible delay time controllability, a voltage controlled inverter is adopted to build the deferential delay cell, which allows fine-tuning of the delay time. The PT calibration circuit is composed of process and temperature monitors, two 2-bit flash ADCs and a lookup table. The monitor circuits sense the PT (Process and Temperature) variations, and the flash ADC converts the data into a digital code. The complete circuits design has been verified under different corners of CMOS 0.18um process technology node.

• 한국전자파학회:학술대회논문집
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• 한국전자파학회 2003년도 종합학술발표회 논문집 Vol.13 No.1
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• pp.496-500
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• 2003

In This paper, a pole-zero optimized design method for multi-layed planar interdigital stripeline linear group delay bandpass filter with tap input port is presented. As a design example, a four-pole group delay filter with center frequency of 2.14GHz, bandwidth of 160MHz, and group delay variation of ${\pm}0.1nS$ for LTCC technology or multilayerd PCB technology is designed. In the design process, as well the whole structure is not necessary to be simulated, and within three times of optimizing process we have good result as well. This design method could be useful for controlling error correction of manufacturing process as well as design stage.

• 대한전기학회논문지
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• 제43권7호
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• pp.1158-1168
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• 1994

A variable structure control scheme(VSCS) with sliding mode that can be applied to the process with input/output(I/O) delay is proposed and its control performances is evaluated. The proposed VSCS with and output feedback scheme comprises a variable structure controller, a servo dynamic for tracking the set-poing, and a Smith predictor for compensating the effects of time delay. The robustness against the parameter variations and external disturbances can be achieved by the proposed VSCS even when the controlled process includes I/O delay. And the desired transient response is obtained by simple adjustment of the coefficients of the switching surface equation.

• Structural Engineering and Mechanics
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• 제82권4호
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• pp.445-458
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• 2022

Some of the control systems used in engineering structures that use sensors and decision systems have some time delay reducing efficiency of the control system or even might make it unstable. In this research, in addition to considering the effect of the time delay in vibration control process, predictive control is used to compensate the time delay. A semi-active vibration control approach with the help of magneto-rheological dampers is implemented. In addition to using fuzzy inference system to determine the appropriate control voltage for MR damper, structural behavior prediction system and specifying future responses are also used such that the time delays occurring within control process are overcome. For this purpose, determination of prediction horizon is conducted for one, five, and ten steps ahead for single degree of freedom structures with periods ranging from 0.1 to 4 seconds, subjected to twenty earthquake excitations. The amount of time delay applied to the control system is 0.1 seconds. The obtained results indicate that for 0.1 second time delay, average prediction error values compared to the case without time delay is 3.47 percent. Having 0.1 second time delay in a semi-active control system reduces its efficiency by 11.46 percent; while after providing the control system with structure behavior prediction, the difference in the results for the control system without time delay is just 1.35 percent on average; indicating a 10.11 percent performance improvement for the control system.

• 한국건설관리학회:학술대회논문집
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• 한국건설관리학회 2003년도 학술대회지
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• pp.426-429
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• 2003

건설공사는 프로젝트의 진행 중 내${\cdot}$외부의 여러 조건의 변경이나 사회적 요구에 따라 초기의 계약과는 다른 많은 변경사항이 발생하게 된다. 이러한 변경사항은 프로젝트 추진과정에서 많은 영향을 미치게 되며, 이로 인하여 발생되는 영향은 대부분 프로젝트의 공기지연으로 나타나게 된다. 건설공사에서 발생하는 공기 지연은 기본적으로 도급자의 면책여부에 따라 공기연장이나 지체상금의 부과 등의 결과로 나타나게 되는데 이러한 사항에 대한 발주자와 도급자의 의견이 대립될 경우 클레임으로 발전하게 된다. 클레임에서 가장 중요한 사항은 공기지연일수의 산정으로서 이는 공기지연 클레임에서 가장 중요한 부분이라고 할 수 있다. 본 연구에서는 공기지연 클레임에서 가장 중요한 자료가 되는 공기지연일수 산정방법의 한 방법으로 계약 초기에 작성된 계획공정표(As-Planned Schedule)와 모든 지연이 포함된 준공공정표(As-Built Schedule including all delays) 그리고 발주자 지연이 제외된 준공공정표(As-Built schedule absent owner delays)를 비교함으로써 각 계약 구성원의 귀책으로 인한 광기 지연일수 산정방법을 제시하고자 한다.