• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.4
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• pp.653-659
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• 2008

This paper describes the design of high power transistor packages using high power chip transistor dies, chip capacitors and a new wire bonding technique. Input impedance variation and output power performances according to wire inductance and resistance for internal matching are also discussed. A multi crossing type(MCT) wire bonding technique is proposed to replace the conventional stepping stone type(SST) wire bonding technique, and eventually to improve the output power performances of high power transistor packages. Using the proposed MCT wire bonding technique, it is possible to design high power transistor packages with highly improved output power compared to SST even the package size is kept to be the same.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.302-317
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• 2017

This paper proposes a new full adder design based on pass-transistor logic that offers ultra-low power dissipation and superior variability together with low transistor count. The pass-transistor logic allows device count reduction through direct logic realization, and thus leads to reduction in the node capacitances as well as short-circuit currents due to the absence of supply rails. Optimum transistor sizing alleviates the adverse effects of process variations on performance metrics. The design is subjected to a comparative analysis against existing designs based on Monte Carlo simulations in a SPICE environment, using the 22-nm CMOS Predictive Technology Model (PTM). The proposed ULP adder offers 38% improvement in power in comparison to the best performing conventional designs. The trade-off in delay to achieve this power saving is estimated through the power-delay product (PDP), which is found to be competitive to conventional values. It also offers upto 79% improvement in variability in comparison to conventional designs, and provides suitable scalability in supply voltage to meet future demands of energy-efficiency in portable applications.

• The KIPS Transactions:PartA
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• v.15A no.2
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• pp.69-74
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• 2008

This paper proposes a structure of low-power MOS current-mode logic circuit with sleep-transistor to reduce the leakage current. The sleep-transistor is used to high-threshold voltage transistor to minimize the leakage current. The $16\;{\times}\;16$ bit parallel multiplier is designed by the proposed circuit structure. Comparing with the conventional MOS current-model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/50. This circuit is designed with Samsung $0.35\;{\mu}m$ CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• Proceedings of the KIEE Conference
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• 1987.11a
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• pp.539-542
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• 1987

This paper presents driving circuits technology to enable high speed drive of MOSFET, IGBT(Insulated Gate Bipolar Transistor) and SIT(Static Induction Transistor). In addition to, it demonstrates application circuits(high frequency resonant type inverters, ultrasonic power supply etc.) using the, developing drive circuits.

• Journal of IKEEE
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• v.12 no.4
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• pp.211-216
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• 2008

This paper proposes an 8${\times}$8 bit parallel multiplier using MOS current-mode logic (MCML) circuit for low power consumption. The proposed circuit has a structure of low-power MOS current-mode logic circuit with sleep-transistor to reduce the leakage current. The sleep-transistor is used to PMOS transistor to minimize the leakage current. Comparing with the conventional MOS current-model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/50. The designed multiplier is achieved to reduce the power consumption by 10.5% and the power-delay-product by 11.6% compared with the conventional MOS current-model logic circuit. This circuit is designed with Samsung 0.35 ${\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.3
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• pp.59-66
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• 2015

In this paper, we propose a method of improving the light-load efficiency of DC-DC buck converter using 4bit SAR-ADC (Successive Approximation ADC) for a LDO or a power transistor size selection technique. The proposed circuit selects power transistor sizes depending on load current so that improves the light-load efficiency of the DC-DC buck converter. For this, we select the power transistor size with a cross point of the switching loss and the conduction loss. Also, when the IC operates in standby mode or sleep mode, a LDO mode is selected for improving the efficiency. The proposed circuit selects power transistor sizes(X1, X2, X4, X8) with 4 bits and its efficiency is higher about the maximum of 25% at the light-load than that of a single transistor size. Input voltage and output voltage are 5V and 3.3V for maximum load currents of 500mA.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.7
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• pp.1363-1374
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• 2009

This paper reviews the characteristics and technical trends in Power MOSFET technology that are leading to improvements in power loss for power electronic system. The silicon bipolar power transistor has been displaced by silicon power MOSFET's in low and high voltage system. The power electronic technology requires the marriage of power device technology with MOS-gated device and bipolar analog circuits. The technology challenges involved in combining power handling capability with finger gate, trench array, super junction structure, and SiC transistor are described, together with examples of solutions for telecommunications, motor control, and switch mode power supplies.

• The KIPS Transactions:PartA
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• v.17A no.3
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• pp.121-126
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• 2010

This paper proposes a low-power MOS current-mode logic circuit with the low voltage swing technology and the high-threshold sleep-transistor. The sleep-transistor is used to high-threshold voltage PMOS transistor to minimize the leakage current. The $16{\times}16$ bit parallel multiplier is designed by the proposed circuit structure. Comparing with the conventional MOS current-model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/104. The proposed circuit is achieved to reduce the power consumption by 11.7% and the power-delay-product by 15.1% compared with the conventional MOS current-model logic circuit in the normal mode. This circuit is designed with Samsung $0.18\;{\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• The Transactions of the Korean Institute of Power Electronics
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• v.12 no.1
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• pp.50-55
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• 2007

In this paper, we present an analytical method that provides fast and efficient evaluation of the conversion efficiency for Two transistor forward (TTF) DC-DC converter In the proposed method, the conduction losses are evaluated by calculating the effective values of the ideal current waveform first and incorporating them into an exact equivalent circuit model of the TTF converter that includes all the parasitic resistances of the circuit components. While the conduction losses are accurately accounted for the diode rectification, the core losses are assumed to be negligible in order to simplify the analysis. The validity and accuracy of the proposed method are verified with experiments on a prototype TTF converter An excellent correlation between the experiments and theories are obtained for the input voltages of 390V, output voltage 12V and maximum power 480W.

• Journal of the Microelectronics and Packaging Society
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• v.30 no.2
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• pp.43-51
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• 2023

In this paper, we introduce the development trends of power devices which is the key component for power conversion system in electric vehicles, and discuss the characteristics of the next-generation wide-bandgap (WBG) power devices. We provide an overview of the characteristics of the present mainstream Si insulated gate bipolar transistor (IGBT) devices and technology roadmap of Si IGBT by different manufacturers. Next, recent progress and advantages of SiC metal-oxide-semiconductor field-effect transistor (MOSFET) which are the most important unipolar devices, is described compared with conventional Si IGBT. Furthermore, due to the limitations of the current GaN power device technology, the issues encountered in applying the power conversion module for electric vehicles were described.