• Title/Summary/Keyword: power MOS

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Design of a Low-Power MOS Current-Mode Logic Parallel Multiplier (저 전력 MOS 전류모드 논리 병렬 곱셈기 설계)

  • Kim, Jeong-Beom
    • Journal of IKEEE
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    • v.12 no.4
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    • pp.211-216
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    • 2008
  • This paper proposes an 8${\times}$8 bit parallel multiplier using MOS current-mode logic (MCML) circuit for low power consumption. The proposed circuit has a structure of low-power MOS current-mode logic circuit with sleep-transistor to reduce the leakage current. The sleep-transistor is used to PMOS transistor to minimize the leakage current. Comparing with the conventional MOS current-model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/50. The designed multiplier is achieved to reduce the power consumption by 10.5% and the power-delay-product by 11.6% compared with the conventional MOS current-model logic circuit. This circuit is designed with Samsung 0.35 ${\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

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Structure of Low-Power MOS Current-Mode Logic Circuit with Sleep-Transistor (슬립 트랜지스터를 이용한 저 전력 MOS 전류모드 논리회로 구조)

  • Kim, Jeong-Beom
    • The KIPS Transactions:PartA
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    • v.15A no.2
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    • pp.69-74
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    • 2008
  • This paper proposes a structure of low-power MOS current-mode logic circuit with sleep-transistor to reduce the leakage current. The sleep-transistor is used to high-threshold voltage transistor to minimize the leakage current. The $16\;{\times}\;16$ bit parallel multiplier is designed by the proposed circuit structure. Comparing with the conventional MOS current-model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/50. This circuit is designed with Samsung $0.35\;{\mu}m$ CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

A Design of Lateral Power MOS with Improved Blocking Characteristics (향상된 항복특성을 위한 수평형 파워 MOS의 설계)

  • Kim, Dae-Jong;Sung, Man-Young;Kang, Ey-Goo
    • 한국컴퓨터산업교육학회:학술대회논문집
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    • 2003.11a
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    • pp.95-98
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    • 2003
  • Power semiconductors are being currently used as a application of intelligent power inverters to a refrigerator, a washing machine and a vacuum cleaner as well as core parts of industrial system. The rating of semiconductor devices is an important factor in decision on the field of application and the forward blocking voltage is one of factors in decision of the rating. The Power MOS device has a merit of high input impedance, short switching time, and stability in temperature as well known. Power MOS devices are mainly used as switches in the field of power electronics, especially the on-state resistance and breakdown voltage are regarded as the most important parameters. Power MOS devices that enable a small size, a light weight, high-integration and relatively high voltage are required these days. In this paper, we proposed the new lateral power MOS which has forward blocking voltage of 250V and contains trench electrodes and verified manufactural possibility by using TSUPREM-4 that is process simulator.

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Feasibility Study on Wind Power Forecasting Using MOS Forecasting Result of KMA (기상청 MOS 예측값 적용을 통한 풍력 발전량 예측 타당성 연구)

  • Kim, Kyoung-Bo;Park, Yun-Ho;Park, Jeong-Keun;Ko, Kyung-Nam;Huh, Jong-Chul
    • Journal of the Korean Solar Energy Society
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    • v.30 no.2
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    • pp.46-53
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    • 2010
  • In this paper the feasibility of wind power forecasting from MOS(Model Output Statistics) was evaluated at Gosan area in Jeju during February to Octoberin 2008. The observed wind data from wind turbine was compared with 24 hours and 48 hours forecasting wind data from MOS predicting. Coefficient of determination of measured wind speed from wind turbine and 24 hours forecasting from MOS was around 0.53 and 48 hours was around 0.30. These determination factors were increased to 0.65 from 0.53 and 0.35 from 0.30, respectively, when it comes to the prevailing wind direction($300^{\circ}\sim60^{\circ}$). Wind power forecasting ratio in 24 hours of MOS showed a value of 0.81 within 70% confidence interval and it also showed 0.65 in 80% confidence interval. It is suggested that the additional study of weather conditions be carried out when large error happened in MOS forecasting.

Design of a Low-Power MOS Monolithic Peak Detector (저전력 MOS 모놀리식 피크 감지기의 설계)

  • 박광민;백경호
    • Proceedings of the IEEK Conference
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    • 2000.06b
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    • pp.217-220
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    • 2000
  • In this paper, A low-power MOS monolithic peak detector is presented. Designed for monolithic and low-power characteristics, this MOS peak detector can be integrated easily on the same chip as a module of large communication systems. The simulation results of this peak detector which was composed with four NMOSs and two capacitors show the power dissipation of 0.972㎽ and the good operations for 2㎓ operating pulse frequency. Therefore, it may be used as a functional block for various signal processing systems.

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Design of a Low-Power MOS Current-Mode Logic Circuit (저 전력 MOS 전류모드 논리회로 설계)

  • Kim, Jeong-Beom
    • The KIPS Transactions:PartA
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    • v.17A no.3
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    • pp.121-126
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    • 2010
  • This paper proposes a low-power MOS current-mode logic circuit with the low voltage swing technology and the high-threshold sleep-transistor. The sleep-transistor is used to high-threshold voltage PMOS transistor to minimize the leakage current. The $16{\times}16$ bit parallel multiplier is designed by the proposed circuit structure. Comparing with the conventional MOS current-model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/104. The proposed circuit is achieved to reduce the power consumption by 11.7% and the power-delay-product by 15.1% compared with the conventional MOS current-model logic circuit in the normal mode. This circuit is designed with Samsung $0.18\;{\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

Linked operation between energy management system(EMS) and market operation system(MOS, CBP) (계통운영시스템(EMS)과 시장운영시스템(MOS,CBP)간 연계운영)

  • Park, Bong-Yong;Kim, Myung-Woong;Ahn, Jae-Seung;Kim, Min-Bae
    • Proceedings of the KIEE Conference
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    • 2009.07a
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    • pp.547_548
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    • 2009
  • 전력거래소에서 전력계통 및 전력시장 운영을 위해 도입한 핵심시스템은 EMS, MOS, CBP 이다. 이 세개 시스템은 각각 고유의 기능을 가진 별도의 시스템으로 구축되었다. 우리나라의 전력시장이 발전경쟁단계에 머무르면서 당초 양방향전력시장용으로 도입된 MOS시스템이 활용되지 못함에 따라 MOS시스템의 실시간 급전기능을 활용해 전력계통 운영의 안정성 및 경제성 향상을 꾀하고자 이 세 개의 시스템을 2006년 10월부터 연계 운영하고 있다. 이를 위해 CBP입찰값을 MOS의 입찰형식으로 변환하기위한 CBP-MOS 입찰변환시스템, 실시간 수요예측을 위한 수요예측 프로그램, MOS와 EMS를 일괄적으로 연계하기 위한 연계Mode, 각 발전기 운전원들에게 발전기의 급전계획값 및 실시간 운전현황을 전송하기 위한 급전지시시스템(MX) 및 전반적인 시스템 연계운영을 종합적으로 감시하기 위한 종합감시시스템 등을 개발하여 운영하고 있다.

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DC voltage control by drive signal pulse-width control of full-bridged inverter

  • Ishikawa, Junichi;Suzuki, Taiju;Ikeda, Hiroaki;Mizutani, Yoko;Yoshida, Hirofumi
    • 제어로봇시스템학회:학술대회논문집
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    • 1996.10a
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    • pp.255-258
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    • 1996
  • This paper describes a DC voltage controller for the DC power supply which is constructed using the full-bridged MOS-FET DC-to-RF power inverter and rectifier. The full-bridged MOS-FET DC-to-RF inverter consisting of four MOSFET arrays and an output power transformer has a control function which is able to control the RF output power when the widths of the pulse voltages which are fed to four MOS-FET arrays of the fall-bridged inverter are changed using the pulse width control circuit. The power conversion efficiency of the full-bridged MOS-FET DC-to-RF power inverter was approximately 85 % when the duty cycles of the pulse voltages were changed from 30 % to 50 %. The RF output voltage from the full-bridged MOS-FET DC-to-RF inverter is fed to the rectifier circuit through the output transformer. The rectifier circuit consists of GaAs schottky diodes and filters, each of which is made of a coil and capacitors. The power conversion efficiency of the rectifier circuit was over 80 % when the duty cycles of the pulse voltages were changed from 30 % to 50 %. The output voltage of the rectifier circuit was changed from 34.7V to 37.6 V when the duty cycles of the pulse voltages were changed from 30 % to 50 %.

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Efficiency Enhancement of Electricity Market by MOS-EMS Interfaced Operation (MOS-EMS 연계활용을 통한 전력시장의 효율개선)

  • Ok, Ki-Youl;Kim, Kwang-In;Kim, Doo-Jung;Kim, Kwang-Chul;Moon, Young-Kwon
    • Proceedings of the KIEE Conference
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    • 2006.07a
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    • pp.363-364
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    • 2006
  • 변동비반영시장(CBP)의 장기화가 예상됨에 따라 전력거래소는 차기 도매전력시장의 운영을 위해 개발된 시장운영시스템(MOS)을 현행급전체계에 활용하는 사업을 추진하고 있다. 이를 위하여 전력거래소는 현 CBP의 비용기반 입찰자료를 MOS의 가격입찰 방식으로 등가적으로 변환하는 입찰변환시스템과 MOS-EMS 연계운영의 적정성을 감시 및 진단하는 시장운영감시시스템을 개발하였다. 또한 MOS의 실시간(5분) 급전계획이 최적으로 수립될 수 있도록 상태추정의 신뢰성 및 수요예측의 정확도를 향상시켰다. 아울러 MOS-EMS 연계운영의 안정성을 검증하기 위해 10단계에 걸친 실계통 실증시험을 성공적으로 종료하였으며, 그 결과 계통운영의 효율성 및 투명성 향상은 물론 연간 260억원 이상의 발전비용 절감효과가 발생함을 입증하였다.

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The Study of Improving Forward Blocking Characteristics for Small Sized Lateral Trench Electrode Power MOSFET using Trench Isolation (수평형 파워 MOSFET에 있어서 트렌치 Isolation 적용에 의한 순방향 항복특성 개선을 위한 새로운 소자의 설계에 관한 연구)

  • Kim, Jin-Ho;Kim, Je-Yoon;Ryu, Jang-Woo;Sung, Man-Young;Kim, Ki-Nam
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2004.07a
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    • pp.9-12
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    • 2004
  • In this paper, a new small sized Lateral Trench Electrode Power MOS was proposed. This new structure, called LTEMOS(Lateral Trench Electrode Power MOS), was based on the conventional lateral power MOS. But the entire electrodes of LTEMOS were placed in trench oxide. The forward blocking voltage of the proposed LTEMOS was improved by 1.5 times with that of the conventional lateral power MOS. The forward blocking voltage of LTEMOS was about 240 V. At the same size, an improvement of the forward blocking voltage of about 1.5 times relative to the conventional MOS was observed by using ISE-TCAD which was used for analyzing device's electrical characteristics. Because all of the electrodes of the proposed device were formed in each trench oxide, the electric field was crowded to trench oxide and punch-through breakdown was occurred, lately.

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