• Journal of Sensor Science and Technology
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• v.16 no.3
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• pp.197-201
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• 2007

The magnetron reactive ion etching (RIE) characteristics of polycrystalline (poly) 3C-SiC grown on $SiO_{2}$/Si substrate by APCVD were investigated. Poly 3C-SiC was etched by $CHF_{3}$ gas, which can form a polymer as a function of side wall protective layers, with additive $O_{2}$ and Ar gases. Especially, it was performed in magnetron RIE, which can etch SiC at a lower ion energy than a commercial RIE system. Stable etching was achieved at 70 W and the poly 3C-SiC was undamaged. The etch rate could be controlled from $20\;{\AA}/min$ to $400\;{\AA}/min$ by the manipulation of gas flow rates, chamber pressure, RF power, and electrode gap. The best vertical structure was improved by the addition of 40 % $O_{2}$ and 16 % Ar with the $CHF_{3}$ reactive gas. Therefore, poly 3C-SiC etched by magnetron RIE can expect to be applied to M/NEMS applications.

• Journal of Sensor Science and Technology
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• v.6 no.6
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• pp.483-490
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• 1997

Thin film Si has been used in sensors, radiation detectors, and solar cells. The carrier mobility of thin film Si influences the device behavior through its frequency response or time response. Since poly-Si shows the higher mobility value, a-Si:H films on Mo substrate were subjected to various crystallization treatments. Consequently, we need to find an appropriate method in mobility measurement before and after the anneal treatment. This paper investigates the carrier mobility improvement with anneal treatments and summarizes the mobility measurement methods of the a-Si:H and poly-Si film. Various techniques were investigated for the mobility determination such as Hall mobility, HS, TOF, SCLC, TFT, and TCO method. We learned that TFT and TCO method are suitable for the mobility determination of a-Si:H and poly-Si film. The measured mobility was improved by $2{\sim}3$ orders after high temperature anneal above $700^{\circ}C$ and grain boundary passivation using an RF plasma rehydrogenation.

• Transactions on Electrical and Electronic Materials
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• v.1 no.2
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• pp.7-11
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• 2000

a-Si:H and poly-Si TFT(thin film transistor) characteristics were investigated using an inverted staggered type TFT. The TFT an as-grown a-Si:H exhibited a low field effect mobility, transconductance, and high gate threshold voltage. The poly-Si films were achieved by using an isothermal and RTA treatment for glow discharge deposited a-Si:H films. The a-Si:H films were cystallized at the various temperature from 600$^{\circ}C$ to 1000$^{\circ}C$. As anneal temperature was elevated, the TFT exhibited increased g$\sub$m/ and reduced V$\sub$ds/. V$\sub$T/. The poly-Si grain boundary passivation with grain boundary trap types and activation energies as a function of anneal temperature. The poly-si TFT showed an improved I$\sub$nm//I$\sub$off/ ratio of 10$\^$6/, reduced gate threshold voltage, and increased field effect mobility by three orders.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.1
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• pp.26-32
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• 2003

Then-channel poly-Si thin-film transistors (poly-Si TFT's) formed by solid phase crystallization (SPC) method on glass were measured to obtain the electrical parameters such as of I-V characteristics, mobility, leakage current, threshold voltage, and subthreshold slope. Then, devices were analyzed to obtain the reliability and appliability on TFT-LCD with large-size and high density. In n-channel poly-Si TFT with 5$\mu\textrm{m}$/2$\mu\textrm{m}$, 8$\mu\textrm{m}$, 30$\mu\textrm{m}$ devices of channel width/length, the field effect mobilities are 111, 116, 125 $\textrm{cm}^2$/V-s and leakage currents are 0.6, 0.1, and 0.02 pA/$\mu\textrm{m}$, respectively. Low threshold voltage and subthreshold slope, and good ON-OFF ratio are shown, as well. Thus. the poly-Si TFT's used by SPC are expected to be applied on TFT-LCD with large-size and high density, which can integrate the display panel and peripheral circuit on a targe glass substrate.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.496-498
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• 2005

We reported that high dielectric hafnium oxide nano-film deposited by thermal atomic layer deposition on the poly-silicon film (poly-Si). The poly -Si film was produced by plasma enhanced chemical vapor deposition and excimer laser annealing. We used the hafniu m chloride ($HfCl_4$) and water as the precursors and analyzed the hafnium oxide film by transmission electron microscope and secondary ion mass spectrometer. Hafnium oxide produced by the ALD method showed very good coverage on the rough surface of poly-Si film. While deposited with 200 cycles, these hafnium oxide films revealed a relatively smooth surface and good uniformity, but the cumulative roughness produced by the incomplete reaction was apparent when the amount of deposition cycle increased to 600 cycles.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.53 no.5
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• pp.237-241
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• 2004

Amorphous silicon (a-Si) films are used in a broad range of solar cell, flat panel display, and sensor. Because of the greater ease of deposition and lower processing temperature, thin films are widely used for thin film transistors (TFTs). However, they have lower stability under the exposure of visible light and because of their low field effect mobility ($\mu$$_{FE}$ ) , less than 1 c $m^2$/Vs, they require a driving IC in the external circuits. On the other hand, polycrystalline silicon (poly-Si) thin films have superiority in $\mu$$_{FE}$ and optical stability in comparison to a-Si film. Many researches have been done to obtain high performance poly-Si because conventional methods such as excimer laser annealing, solid phase crystallization and metal induced crystallization have several difficulties to crystallize. In this paper, a new crystallization process using a molybdenum substrate has been proposed. As we use a flexible substrate, high temperature treatment and roll-to-roll process are possible. We have used a high temperature process above 75$0^{\circ}C$ to obtain poly-Si films on molybdenum substrates by a rapid thermal annealing (RTA) of the amorphous silicon (a-Si) layers. The properties of high temperature crystallized poly-Si studied, and poly-Si has been used for the fabrication of TFT. By this method, we are able to achieve high crystal volume fraction as well as high field effect mobility.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.12
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• pp.761-767
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• 1999

Poly-Si TFTs(polycrystalline silicon thin film transistors) fabricated on a low cost glass substrate have attracted a considerable amount of attention for pixel elements and peripheral driving circuits in AMLCS(active matrix liquid crystal display). In order to apply poly-Si TFTs for high resolution AMLCD, a high operating frequency and reliable circuit performances are desired. A new poly-Si TFT with CLBT(counter doped lateral body terminal) is proposed and fabricated to suppress kink effects and to improve the device stability. And this proposed device with BC(buried channel) is fabricated to increase ON-current and operating frequency. Although the troublesome LDD structure is not used in the proposed device, a low OFF-current is successfully obtained by removing the minority carrier through the CLBT. We have measured the dynamic properties of the poly-Si TFT device and its circuit. The reliability of the TFTs and their circuits after AC stress are also discussed in our paper. Our experimental results show that the BC enables the device to have high mobility and switching frequency (33MHz at $V_{DD}$ = 15 V). The minority carrier elimination of the CLBT suppresses kink effects and makes for superb dynamic reliability of the CMOS circuit. We have analyzed the mechanism in order to see why the ring oscillators do not operate by analyzing AC stressed device characteristics.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.93-93
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• 2008

This paper presents the Raman scattering characteristics of poly (polycrystalline) 3C-SiC thin films deposited on AlN buffer layer by atmospheric pressure chemical vapor deposition (APCVD) using hexamethyldisilane (MHDS) and carrier gases (Ar + $H_2$).The Raman spectra of SiC films deposited on AlN layer of before and after annealings were investigated according to the growth temperature of 3C-SiC. Two strong Raman peaks, which mean that poly 3C-SiC admixed with nanoparticle graphite, were measured in them. The biaxial stress of poly 3C-SiC/AlN was calculated as 896 MPa from the Raman shifts of 3C-SiC deposited at $1180^{\circ}C$ on AlN of after annealing.

• Transactions on Electrical and Electronic Materials
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• v.10 no.4
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• pp.131-134
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• 2009

The electrical properties and the microstructure of nitrogen-doped poly 3C-SiC films used for micro thermal sensors were studied according to different thicknesses. Poly 3C-SiC films were deposited by LPCVD (low pressure chemical vapor deposition) at $900^{\circ}C$ with a pressure of 4 torr using $SiH_2Cl_2$ (100%, 35 sccm) and $C_2H_2$ (5% in $H_2$, 180 sccm) as the Si and C precursors, and $NH_3$ (5% in $H_2$, 64 sccm) as the dopant source gas. The resistivity of the poly SiC films with a 1,530 ${\AA}$ thickness was 32.7 ${\Omega}-cm$ and decreased to 0.0129 ${\Omega}-cm$ at 16,963 ${\AA}$. The measurement of the resistance variations at different thicknesses were carried out within the $25^{\circ}C$ to $350^{\circ}C$ temperature range. While the size of the resistance variation decreased when the films thickness increased, the linearity of the resistance variation improved. Micro heaters and RTD sensors were fabricated on a $Si_3N_4$ membrane by using poly 3C-SiC with a 1um thickness using a surface MEMS process. The heating temperature of the SiC micro heater, fabricated on 250 ${\mu}m$${\times}$250 ${\mu}m$ $Si_3N_4$ membrane was $410^{\circ}C$ at an 80 mW input power. These 3C-SiC heaters and RTD sensors, fabricated by surface MEMS, have a low power consumption and deliver a good long term stability for the various thermal sensors requiring thermal stability.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.3
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• pp.206-211
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• 2005

The device makers want to make higher density chips on the wafer through scale-down. The change of WSix/poly-Si gate film thickness is one of the key issues under 100 nm device structure. As a new device etching process is applied, end point detection(EPD) time delay was occurred in DPS+ poly chamber of Applied Materials. This is a barrier of device shrink because EPD time delay made physical damage on the surface of gate oxide. To investigate the EPD time delay, the experimental test combined with OES(Optical Emission Spectroscopy) and SEM(Scanning Electron Microscopy) was performed using patterned wafers. As a result, a EPD delay time is reduced by a new chamber seasoning and a new wavelength line through plasma scan. Applying a new wavelength of 252 nm makes it successful to call corrected EPD in WSix/poly-Si stack-down gate etching in the DPS+ poly chamber for the current and next generation devices.