• Transactions on Electrical and Electronic Materials
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• v.17 no.2
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• pp.113-117
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• 2016

Temperature dependent reverse-bias current-voltage (I-V) characteristics in Cu Schottky contacts to oxygen plasma treated n-InP were investigated. For untreated sample, current transport mechanisms at low and high temperatures were explained by thermionic emission (TE) and TE combined with barrier lowering, respectively. For plasma treated sample, experimental I-V data were explained by TE or TE combined with barrier lowering models at low and high temperatures. However, the current transport was explained by a thermionic field emission (TFE) model at intermediate temperatures. From X-ray photoemission spectroscopy (XPS) measurements, phosphorus vacancies (VP) were suggested to be generated after oxygen plasma treatment. V_P possibly involves defects contributing to the current transport at intermediate temperatures. Therefore, minimizing the generation of these defects after oxygen plasma treatment is required to reduce the reverse-bias leakage current.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.11a
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• pp.17-20
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• 2000

This study is about a retrograde triple well employed in the Cell tr. of next DRAM and flash memory. Triple well structure is formed deep n-well under the light p-well using MeV ion implantation. MeV P implanted deep n-well was observed to show greatly improved characteristics of electrical isolation and soft error. Junction leakage current, however, showed a critical behavior as a function of implantation and annealing conditions. {311} defects were observed to be responsible for the leakage current. {311} defects were generated near the R$\_$p/ (Projected range) region and grown upward to the surface during annealing. This is study on the defect behavior in device region as a function of implantation and annealing conditions.

• Nuclear Engineering and Technology
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• v.8 no.1
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• pp.29-40
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• 1976

An investigation on the effect of electrostatic drift field which can bring an additional aid to the photogenerated carrier collection in one side of the silicon solar cell has been carried out. The drift field was produced by the gradient of boron concentration in the p-type side in virtue of the strain compensation due to the tin dopant. A new method of ion implantation which is based on the principle of chiefly radiation-enhanced diffusion is adopted for forming the p-n junction in the solar cell. The open circuit voltage and the conversion efficiency of the ion-implanted silicon solar cell sample can be figured out to be 0.44 V and 5%, respectively.

• Journal of Power Electronics
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• v.11 no.2
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• pp.188-193
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• 2011

A highly efficient AC-DC converter for small wind power generation systems using a brushless DC generator (BLDCG) is presented in this paper. The market standard AC-DC converter for a BLDCG consists of a three-phase diode rectifier and a boost DC-DC converter, which has an IGBT and a fast recovery diode (FRD). This kind of two-stage solution basically suffers from a large amount of conduction loss and the efficiency greatly decreases under a light load, or at a low current, because of the switching devices with a P-N junction. In order to overcome this low efficiency, especially at a low current, a three-phase bridgcless converter consisting of three upper side FRDs and three lower side Super Junction FETs is presented. In the overall operating speed region, including the cut-in speed, the efficiency of the proposed converter is improved by up to 99%. Such a remarkable result is validated and compared with conventional solutions by calculating the power loss based on I-V curves and the switching loss data of the adopted commercial switches and the current waveforms obtained through PSIM simulations.

• Korean Journal of Materials Research
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• v.13 no.6
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• pp.398-403
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• 2003

Shallow $p^{＋}$ n junction was formed using a ULE(ultra low energy) implanter. Deactivation phenomena were investigated for the shallow source/drain junction based on measurements of post-annealing time and temperature following the rapid thermal annealing(RTA) treatments. We found that deactivation kinetics has two regimes such that the amount of deactivation increases exponentially with annealing temperature up to $850^{\circ}C$ and that it decreases linearly with the annealing temperature beyond that temperature. We believe that the first regime is kinetically limited while the second one is thermodynamically limited. We also observed "transient enhanced deactivation", an anomalous increase in sheet resistance during the early stage of annealing at temperatures higher than X$/^{\circ}C$. Activation energy for transient enhanced deactivation was measured to be 1.75-1.87 eV range, while that for normal deactivation was found to be between 3.49-3.69 eV.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.381-382
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• 2018

Subthreshold swings (SSs) and on-currents of four types of junctionless nanowire tunnel field-effect transistor(JLNW-TFET) are observed. Ge-Si structure for the source-channel junction has the highest drive current among Si-Si, Si-Ge, and Ge-Ge junction, and the drive current increases up to 1000 times compared to others. Minimum SS of Si-Si junction is reduced by up to 5 times more than others.

• Journal of Satellite, Information and Communications
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• v.9 no.3
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• pp.15-21
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• 2014

An electrostatic discharge (ESD) protection device, so called, N-type embedded silicon controlled rectifier (NESCR), was analyzed for high voltage operating I/O applications. A conventional NESCR standard device shows typical SCR-like characteristics with extremely low snapback holding voltage, which may cause latch-up problem during normal operation. However, our modified NESCR_CPS_PPW device with proper junction/channel engineering such as counter pocket source (CPS) and partial P-well structure demonstrates highly latch-up immune current-voltage characteristics with high snapback holding voltage and on-resistance.

• 전기의세계
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• v.26 no.5
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• pp.83-89
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• 1977

This paper described the minority carrier lifetime in Si epitaxial layer, and also the voltage (V) versus current (I) characteristics of high resistivity Si epitaxial layer0substrate junction. The measured lifetime in Si epi-layer was much shorter than in bulk, and the temperature dependence of lifetime was found to agree well with Shockley-Read model of recombination which applies to high resistivity n-type materials. The V-I curve showed; an ohmic region (I.var.V), a sublinear region (I.var.V$^{1}$2/), a space charge limited current region (I.var.V$^{2}$), and finally a negative resistance region. We investigated these phenomena by the theory of the relaxation semiconductor.

• 전기의세계
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• v.30 no.10
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• pp.645-654
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• 1981

A technique has been proposed for fabricating a submicron channel vertical V-groove JFET using standard photolithography. A finite element numerical simulation of the V-groove JFET operation was performed using a FORTRAN progrma run on a Cyber-174 computer. The numerical simulation predicts pentode like common source output characteristics for the p$^{+}$n Vertical V-groove JFET with maximum transconductance representing approximately 6 precent of the zero bias drain conductance value and markedly high drain conductance at large drain voltages. An increase in the acceptor concentration of the V-groove JFET gate was observed to cause a significant increase in the transconductance of the device. Therefore, as above mentioned, this paper is study on the analysis of a Vertical V-groove Junction Field Effect Transistor with Finite Element Method.d.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.8
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• pp.501-504
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• 2014

This paper was developed and described core-process to implement low on resistance which was the most important characteristics of SJ (super junction) MOSFET. Firstly, using process-simulation, SJ MOSFET optimal structure was set and developed its process flow chart by repeated simulation. Following process flow, gate level process was performed. And source and drain level process was similar to genral planar MOSFET, so the process was the same as the general planar MOSFET. And then to develop deep trench process which was main process of the whole process, after finishing photo mask process, we developed deep trench process. We expected that developed process was necessary to develop SJ MOSFET for automobile semiconductor.