• Journal of the Korean Ceramic Society
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• v.34 no.3
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• pp.314-322
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• 1997

The thin film processing and the applicability as a IMD material of SiO2 aerogels providing ultralow dielec-tric properties were studied. The SiO2 aerogel films with 0.5g/㎤ density (78% porosity) and 4000~21000$\AA$ thickness could be prepared at 25$0^{\circ}C$ and 1160 psig by supercritical drying of wet-gel films, which were spin-coated at the spin rate of 1000~7000 rpm on p-Si(111) wafer under the isopropanol atmosphere. The optimum viscosity of polymeric SiO2 sols for spin coating was in the range of 10~14 cP. The main fac-tors being able to control the film thickness and microstructures were found to be sol concentration, spin rpm, and aging time of wet-gel films. The dielectric constant of the SiO2 aerogel thin film was around 2.0 low enough to be applied to the next generation semiconductor device beyond the giga level.

• Solar Energy
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• v.11 no.1
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• pp.41-49
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• 1991

In this study, the (P)SiC/(N)Si solar cell is fabricated by the vacuum evaporation method with the substrate temperature at about $200{\pm}5[5^{\circ}C]$ and its characteristics are investigated. The optimal thickness of $1.2[{\mu}m]$ of SiC film is derived from the relation between film thickness and conversion efficiency. The characteristics of solar cells are improved by the annealing. The optimum annealing temperature and duration are $420[^{\circ}C]$ and 12[min], respectively it is shown that the peak values of spectral response are shifted to the long wavelength region with increasing the annealing temperature. The X-ray diffraction patterns and the scanning electron micrographs show the grain grow thin SiC film as the annealing temperature and time is increased. The best conversion efficiency is 11.7[%] for a $2.5{\times}1[cm^2]$ cell.

• Journal of the Korean Institute of Telematics and Electronics
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• v.3 no.2
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• pp.2-9
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• 1966

fabricating processes of silicon planar n-p-n transistors are described. These processes include materical preparation, oxidation, photoresist, boron diffusion, phosphorous diffusion, and aluminium metalizing. Boron layer has been diffused in n type silicon from B2O3-SiO2 source using the box method, Phosporous layer has been diffused from P2O5-SiO2 source with the same method. The planar diodes are also fabricated by the processes described above.

• The Journal of Natural Sciences
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• v.5 no.2
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• pp.75-80
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• 1992

The objective of this study is to investigate the effect of dispersion of silicon nitride powder with 5wt% $A1_2$$O_3$ and 5wt% $Y_2$$O_3$ on the microstructure of a sintered body. $Si_3$$N_4$ powder was dispered in a distilled water with varing pH.Zeta potential was measured and the dispersion states were directly observed by SEM. Green bodies were obtained by slip-casting and fired at $1750^{\circ}C$ for 1 hr. Microstructures of fired specimens were observed by SEM. The result were that the specimen prepared from the dispersions with pH 5 and 10 showed the best densification.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.198-198
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• 2010

The low-k SiOCH thin films were prepared by CCP-PECVD method using BTMSM(Bis-trimethylsilylmethane) precursors deposited on p-Si wafer. The structural complexity originate the complex refractive constants of the films, and resulted the elliptical polarization of the incident linearly polarized light source of Xe-ramp in the range from 190nm to 2100nm. Phase difference and amplitude ratio between s wave and p wave propagating through SiOCH thin film was studied. After annealing, the amplitude of p wave was reduced more than s wave, and phase difference between p and s wave was also reduced.

• Journal of Information Display
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• v.6 no.4
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• pp.6-10
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• 2005

The dependence of hysteresis characteristics in low temperature poly-Si (LTPS) thin film transistors (TFTs) on the gate-source voltage (Vgs) or the drain-source voltage (Vds) bias is investigated and discussed. The hysteresis levels in both p-type and n-type LTPS TFTs are independent of Vds bias but increase as the sweep range of Vgs increases. It has been found that the hysteresis in both p-type and n-type LTPS TFTs originated from charge trapping and de-trapping in the channel region rather than at the source/drain edges.

• Journal of the Korean Society for Heat Treatment
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• v.26 no.5
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• pp.225-232
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• 2013

The influence of aging treatment, addition elements and rolling reduction ratio on the microstructure, mechanical, electrical and bendability properties of Cu-Ni-Si-P-x (x = Fe, Sn, Zn) alloys for connector material application was investigated. SEM/EDS analysis exhibited that Ni2-Si precipitates with a size of 20~100 nm were distributed in grains. Fe, Sn, Zn elemnets in Cu-Ni-Si-P alloy imporved the mechanical strength but it was not favor in increasing of electrical conductivity. As higher final rolling reduction ratio, the strength and electrical conductivity is increased after aging treatment, but it indicated excellent bendability. Especially, Cu-2Ni-0.4Si-0.5Sn-0.1Fe-0.03P alloy show the tensile strength value of 700MPa and the electrical conductivity was observed to reach a maximum of 40%IACS. It is optimal for lead frame and connector.

• Proceedings of the KIEE Conference
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• 2004.07c
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• pp.1694-1696
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• 2004

$Si_3N_4$ 박막을 동일한 공정 파라메터로 저압 화학기상증착법(LPCVD)으로 증착하고, IS, LOCOS- IS 및 ISFET의 세 가지 각각 다른 구조로 하여 용약 중 pH 농도 감지용 센서소자를 제작하였다. 이 세 가지 다른 센서소자에 대하여 pH 농도변화에 따른 감지도, 감지특성곡선의 선형성, 히스테리시스 등 주요 특성을 각각 조사한 후 비교 분석하였다. LOCOS-IS 구조의 pH 센서는 ISFET 구조의 pH 센서와 유사한 우수한 제반 pH 감지특성을 보였으나, 간단한 IS 구조의 pH 센서는 이들에 비해 상대적으로 열악한 pH 감지특성을 보였다. 동일공정으로 제작된 Si3N4 박막으로 제작되었음에도 불구하고 간단한 IS 구조의 pH 센서의 비교적 열악한 특성을 보이는 원인을 규명하기 위하여, pH 농도 변화에 따른 C-V특성 변화에 의한 pH 감지특성 조사시의 IS 및 LOCOS-IS 구조의 정전용량의 변화를 비교하고 고찰하였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.6
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• pp.377-385
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• 2018

For the investigation of dopant profiles in implanted $Si_{1-x}Ge_x$, the implanted B and As profiles are measured using SIMS (secondary ion mass spectrometry). The fundamental ion-solid interactions of implantation in $Si_{1-x}Ge_x$ are discussed and explained using SRIM, UT-marlowe, and T-dyn programs. The annealed simulation profiles are also analyzed and compared with experimental data. In comparison with the SIMS data, the boron simulation results show 8% deviations of $R_p$ and 1.8% deviations of ${\Delta}R_p$ owing to relatively small lattice strain and relaxation on the sample surface. In comparison with the SIMS data, the simulation results show 4.7% deviations of $R_p$ and 8.1% deviations of ${\Delta}R_p$ in the arsenic implanted $Si_{0.2}Ge_{0.8}$ layer and 8.5% deviations of $R_p$ and 38% deviations of ${\Delta}R_p$ in the $Si_{0.5}Ge_{0.5}$ layer. An analytical method for obtaining the dopant profile is proposed and also compared with experimental and simulation data herein. For the high-speed CMOSFET (complementary metal oxide semiconductor field effect transistor) and HBT (heterojunction bipolar transistor), the study of dopant profiles in the $Si_{1-x}Ge_x$ layer becomes more important for accurate device scaling and fabrication technologies.

• Applied Microscopy
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• v.26 no.1
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• pp.95-104
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• 1996

A comprehensive methodology to characterize the interfacial reaction products of $SiC_p/2024$ Al composites is introduced on the basis of the experimental results obtained using XRD, SEM and TEM. XRD performed on the electrochemically extracted $SiC_p$ and bulk $SiC_p/2024$ Al composite have shown that the interfacial reaction products consist of $Al_{4}C_3$ having hexagonal crystallographic structure, pure eutectic Si having diamond cubic crystallographic structure, and $CuAl_2$, having tetragonal crystalloraphic structure, respectively. According to the images observed by SEM, $Al_{4}C_3$, which has been reported to have needle shape, has a hexagonal platelet-shape and eutectic Si is found to have a dendritic shape. In addition eutectic $CuAl_2$, was observed to form near interface and/or along the grain boundaries. In order to confirm the results obtained by XRD, the primitive cell volume and reciprocal lattice height of such interfacial reaction products were calculated using the data obtained from convergent beam electron diffraction (CBED) patterns, and then compared with theoretical values.