• Journal of applied mathematics & informatics
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• v.8 no.2
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• pp.659-668
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• 2001

Let S(z) be a power series with operator coefficients such that multiplication by S(z) is an everywhere defined transformation in the square summable power series C(z). In this paper we show that there exists a reproducing kernel Krein space which is state space of extended canonical linear system with transfer function S(z). Also we characterize the reproducing kernel function of the state space of a linear system.

• Honam Mathematical Journal
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• v.33 no.3
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• pp.301-310
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• 2011

In this paper, we construct the sets of fuzzy matrix pairs. These sets are naturally occurred at the extreme cases for the zero-term rank inequalities derived from the multiplication of fuzzy matrix pairs. We characterize the linear operators that preserve these extreme sets of fuzzy matrix pairs.

• Journal of applied mathematics & informatics
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• v.16 no.1_2
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• pp.461-468
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• 2004

Let W(z) be a power series with operator coefficients such that multiplication by W(z) is contractive in C(z). The overlapping space $L(\varphi)$ of H(W) in C(z) is a Herglotz space with Herglotz function $\varphi(z)$ which satisfies $\varphi(z)+\varphi^＊(z^{-1})=2[1-W^{*}(z^{-1})W(z)]$. The identity ${}_{L(\varphi)}={-}_{H(W)}$ holds for every f(z) in $L(\varphi)$ and for every vector c.

• Honam Mathematical Journal
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• v.29 no.4
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• pp.511-521
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• 2007

Let S($z_1$, $z_2$) be a power series with operator coefficients such that multiplication by 5($z_1$, $z_2$) is a contractive transformation in the Hilbert space $\mathbf{H}_2$($\mathbb{D}^2$, C). In this paper we show that there exists a Hilbert space D($\mathbb{D}$,$\bar{S}$) which is the state space of extended canonical linear system with a transfer fucntion $\bar{S}$(z).

• Journal of the Korean Mathematical Society
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• v.54 no.3
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• pp.967-986
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• 2017

We give the necessary condition for an operator defined on a cartesian product of $c_0(\mathcal{X})$ spaces to be summing or dominated and we show that for the multiplication operators this condition is also sufficient. By using these results, we show that ${\Pi}_s(c_0,{\ldots},c_0;c_0)$ contains a copy of $l_s(l^m_2{\mid}m{\in}\mathbb{N})$ for s > 2 or a copy of $1_s(l^m_1{\mid}{\in}\mathbb{N})$, for any $l{\leq}S$ < ${\infty}$. Also ${\Delta}_{s_1,{\ldots},s_n}(c_0,{\ldots},c_0;c_0)$ contains a copy of $l_{{\upsilon}_n(s_1,{\ldots},s_n)}$ if ${\upsilon}_n(s_1,{\ldots},s_n){\leq}2$ or a copy of $l_{{\upsilon}_n(s_1,{\ldots},s_n)}(l^m_2{\mid}m{\in}\mathbb{N})$ if 2 < ${\upsilon}_n(s_1,{\ldots},s_n)$, where ${\frac{1}{{\upsilon}_n(s_1,{\ldots},s_n})}={\frac{1}{s_1}}+{\cdots}+{\frac{1}{s_n}}$. We find also the necessary and sufficient conditions for bilinear operators induced by some method of summability to be 1-summing or 2-dominated.

• Journal of the Korea Society of Computer and Information
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• v.12 no.3
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• pp.37-50
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• 2007

In this paper, we designed and implementation of the high speed neuron processor for real time object recognition in the making automatic system. and we designed of the PE(Processing Element) used residue number system without carry propagation for the high speed operation. Consisting of MAC(Multiplication and Accumulation) operator using residue number system and sigmoid function operator unit using MAC(Mixed Radix conversion) is designed. The designed circuits are descript by C language and VHDL(Very High Speed Integrated Circuit Hardware Description Language) and synthesized by compass tools and finally, the designed processor is fabricated in $0.8{\mu}m$ CMOS process. we designed of MAC operation unit and sigmoid proceeding unit are proved that it could run time 0.6nsec on the simulation and improved to the speed of the three times and decreased to hardware size about 50%, each order. The designed neuron processor can be implemented of the object recognition in making automatic system with desired real time processing.

• School Mathematics
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• v.7 no.2
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• pp.139-168
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• 2005

The purpose of this study is to investigate children's informal knowledge of the fractional multiplication and to develop a teaching material connecting the informal and the formal knowledge. Six lessons of the pre-teaching material are developed based on literature reviews and administered to the 7 students of the 4th grade in an elementary school. It is shown in these teaching experiments that children's informal knowledge of the fractional multiplication are the direct modeling of using diagram, mathematical thought by informal language, and the representation with operational expression. Further, teaching and learning methods of formalizing children's informal knowledge are obtained as follows. First, the informal knowledge of the repeated sum of the same numbers might be used in (fractional number)$\times$((natural number) and the repeated sum could be expressed simply as in the multiplication of the natural numbers. Second, the semantic meaning of multiplication operator should be understood in (natural number)$\times$((fractional number). Third, the repartitioned units by multiplier have to be recognized as a new units in (unit fractional number)$\times$((unit fractional number). Fourth, the partitioned units should be reconceptualized and the case of disjoint between the denominator in multiplier and the numerator in multiplicand have to be formalized first in (proper fractional number)$\times$(proper fractional number). The above teaching and learning methods are melted in the teaching meterial which is made with corrections and revisions of the pre-teaching meterial.

• Journal of the Korea Society of Computer and Information
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• v.10 no.5 s.37
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• pp.109-114
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• 2005

Twofish cryptographic algorithm is concise algorithm itself than Rijndael cryptographic algorithm as AES, and easy of implementation is good, but the processing speed has slow shortcoming. Therefore this paper designed improved MDS block to improve Twofish cryptographic algorithm's speed. Problem of speed decline by a bottle-neck Phenomenon of the Processing speed existed as block that existing MDS block occupies Twofish cryptosystem's critical path. To reduce multiplication that is used by operator in MDS block this Paper removed a bottle-neck phenomenon and low-speed about MDS itself using LUT operation and modulo-2 operation. Twofish cryptosystem including modified MDS block designed by these result confirmed that bring elevation of the processing speed about 10$\%$ than existing Twofish cryptosystem.

• School Mathematics
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• v.11 no.4
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• pp.685-706
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• 2009

This dissertation is aimed to investigate the reason why a contextualization is needed to help the meaningful teaching-learning concerning multiplications and divisions of fractions, the way to make the contextualization possible, and the methods which enable us to use it effectively. For this reason, this study intends to examine the differences of situations multiplying or dividing of fractions comparing to that of natural numbers, to recognize the changes in units by contextualization of multiplication of fractions, the context is set which helps to understand the role of operator that is a multiplier. As for the contextualization of division of fractions, the measurement division would have the left quantity if the quotient is discrete quantity, while the quotient of the measurement division should be presented as fractions if it is continuous quantity. The context of partitive division is connected with partitive division of natural number and 3 effective learning steps of formalization from division of natural number to division of fraction are presented. This research is expected to help teachers and students to acquire meaningful algorithm in the process of teaching and learning.

• Journal of Advanced Navigation Technology
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• v.22 no.2
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• pp.154-162
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• 2018

The multiplier circuit is necessary to estimate degradation status of electronic cards in nuclear power plant, but its accuracy is not easy in processing those functions to multiply two input signals. What is important in multiplier circuit is that the multiplication result must be accurate and its linearity must be perfect. We developed and proposed excellent linearity multiplier circuit using operational amplifiers and transistor characteristics, and then proved its validity in this paper. We have made efforts to eliminate nonlinearity components of semiconductors with this circuit in order to ensure excellent linearity of developed multiplier circuit. We conducted multiplication operations through simulation, applying adequate values to each component in order to verify the circuit composed of that method. We showed step-by-step output signals, and then compared the logical analyses and measuring results as simulation results. We confirmed that this method is superior to existing multiplication or linearity.