• Journal of Power Electronics
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• v.9 no.3
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• pp.438-446
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• 2009

The performance of direct torque controlled (DTC) interior permanent magnet (IPM) machines is poor at low speeds due to a few reasons, namely limited accuracy of stator voltage acquisition and the presence of offset and drift components in the acquired signals. Due to factors such as forward voltage drop across switching devices in the three phase inverter and dead-time of the devices, the voltage across the machine terminals differ from the reference voltage vector used to estimate stator flux and electromagnetic torque. This can lead to instability of the IPM drive during low speed operation. Compensation schemes for forward voltage drops and dead-time are proposed and implemented in real-time control, resulting in improved performance of the space vector modulated DTC IPM drive, especially at low speeds. No additional hardware is required for these compensators.

• Proceedings of the Acoustical Society of Korea Conference
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• 1998.06e
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• pp.177-180
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• 1998

높은 Q가 요구되는 고주파 신호 처리용 필터 설계에서는 흔히 SC 필터를 사용하고 있다. 처리하고자 하는 신호가 고주파수이고, 선택도 Q 값이 매우 높은 경우에는, SC 필터에 사용하는 증폭기의 성능이 빠르고, 직류 성분 이득이 커야만 한다. 이와 같은 속도와 이득이 요구됨에 따라 일반적인 범용 증폭기는 이득이 충분치 못하여 사용이 제한되고, 설사 범용 증폭기를 이용하여 필터를 구성하였다 해도 그 특성에 많은 제한을 줄 수밖에 없다. 또한 GaAS MESFET op amp의 경우, 최근의 논문에서도 60[dB] 이상의 이득이 제안된 바 없으므로, 필터 구성시 또 다른 설계 기술이 요구된다. 따라서 본 논문에서는 GaAS MESFET 능동 SC 적분기의 유한한 이득과 offset 전압을 보정한 새로운 구조의 적분기를 제안한다.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.65 no.1
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• pp.18-24
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• 2016

In order to service restoration and enhance power system reliability, a number of impedance based fault location algorithms have been developed for fault locating in a transmission line. This paper presents an advanced impedance-based fault location algorithms in a two-ended sources transmission line to reduce the DC offset error effects. This fault location algorithm uses of the GPS time synchronized voltage and current signals from the local and remote terminal. The algorithm uses an advanced DC offset removal filter. A series of test results using ATPdraw simulation data show the performance effectiveness of the proposed algorithm. The proposed algorithm is valid for a two-end sources transmission network.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.12
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• pp.40-48
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• 1998

An offset compensation scheme for rail-to-rail CMOS op-amps with complementary input stages is presented. Two auxiliary amplifiers are used to compensate for the offsets of NMOS and PMOS differential input stages, and ping-pong control is employed for continuous-time operation. A 3V offset-compensated rail-to-rail CMOS op-amp has been designed and fabricated using a 0.8$\mu\textrm{m}$ single-poly, double-metal CMOS process. Measurement results show that offsets are reduced about 20 times by this scheme.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.50 no.10
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• pp.489-493
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• 2001

The on-current of offset and LDD structured devices in slightly decreased while the off-current are remarkably reduced and almost constant independent of gate and drain voltage because offset and LDD regions behave as a series resistance and reduce the lateral electric field in the drain depletion. Degradation of these devices is dependent upon the offset and LDD length rather than doping concentration in these regions. Also, degradation mechanism has been related to the interface generation rather than the hot carrier injection into gate oxide.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.4
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• pp.622-629
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• 2001

An engineering model VCO with a good phase noise for Ku-band satellite transponder is designed using a nonlinear design methodology. It generates frequencies from 1,745 and 1,755 MHz with control voltages from 0 to 5 V DC. This unit requires 7 mA of current from 5 V DC supply voltage. Phase noise characteristics of the manufactured VCO exhibit -114 dBc/Hz @10 kHz offset and -131 dBc/Hz @100 kHz of offset and its output power is 5 dBm.

• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.483-484
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• 2007

In this paper, we describe a chip design technique for instrumentation amplifier using a nested-chopping technique. Conventional chopping technique uses a pair of chopper, but nested chopping technique uses two pairs of chopper to reduce residual offset and 1/f noise. The inner chopper pair removes the 1/f noise, while the outer chopper pair reduces the residual offset. Our instrumentation amplifier using a nested chopping technique has residual offset under 100 nV. We also implement very low frequency filter. Since this filter needs very large RC time constant, we use a technique named 'diode connected PMOS' to increase R with small die area. The total power consumption is 3.1 mW at the supply voltage of 3.3V with the 0.35um general CMOS technology. The die area of implemented chip was $530um{\times}300um$.

• Journal of the Korean Vacuum Society
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• v.12 no.4
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• pp.239-250
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• 2003

The reliability degradation phenomena in the SiGe hetero-junction bipolar transistor (HBT) are investigated in this review. In the case of the SiGe HBT the decrease of the current gain, the degradation of the AC characteristics, and the offset voltage are frequently observed, which are attributed to the emitter-base reverse bias voltage stress, the transient enhanced diffusion, and the deterioration of the base-collector junction due to the fluctuation in fabrication process, respectively. The reverse-bias stress on the emitter-base junction causes the recombination current to rise, increasing the base current and degrading the current gain, because hot carriers formed by the high electric field at the junction periphery generate charged traps at the silicon-oxide interface and within the oxide region. Because of the enhanced diffusion of the dopants in the intrinsic base induced by the extrinsic base implantation, the shorter distance between the emitter-base junction and the extrinsic base than a critical measure leads to the reduction of the cut-off frequency ($f_t$) of the device. If the energy of the extrinsic base implantation is insufficient, the turn-on voltage of the collector-base junction becomes low, in the result, the offset voltage appears on the current-voltage curve.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.24 no.9
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• pp.108-117
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• 2010

The main contents of this paper are the PQM system construction case and distribution system harmonic voltage analysis. The PQM system has constructed by KEPCO in order to investigate power quality of distribution power system for new power quality standard of KEPCO. In result, we have confirmed that voltage harmonic measurement value of the high voltage contract customer 8 households is suitable the KEPCO harmonic standard tentative plan. And the voltage harmonic value of distribution line end side is not always more high than source side by harmonic current offset effect. In the future, acquired data by season, region, load from the PQMS will be used on the resonable harmonic standard enactment in KEPCO.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.2
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• pp.471-475
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• 2010

This paper presents a frequency synthesizer using low voltage active inductor VCO(Voltage Controlled Oscillator). The low voltage active inductor VCO with feedback resistor increases its equivalent inductance and the quality-factor(Q). Under certain conditions, the low voltage active inductor with feedback resistor generates a negative resistance at the input. In this paper, the conditions for negative resistance are obtained by small signal analysis. The designed low voltage active inductor VCO covers a frequency band between 1059MHz and 1223MHz. The measured phase noise at 1.178GHz is -81.8dBc/Hz at 1MHz offset.