Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)
- 2007.10a
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- Pages.483-484
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- 2007
A Design of Instrumentation Amplifier using a Nested-Chopping Technique
Nested-chopping 기법을 이용한 Instrumentation Amplifier 설계
- Lee, Jun-Gyu (Dept. of Electronic Engineering, Sogang University) ;
- Burm, Jin-Wook (Dept. of Electronic Engineering, Sogang University) ;
- Lim, Shin-Il (Dept. of Computer Engineering, Seokyeong University)
- Published : 2007.10.26
Abstract
In this paper, we describe a chip design technique for instrumentation amplifier using a nested-chopping technique. Conventional chopping technique uses a pair of chopper, but nested chopping technique uses two pairs of chopper to reduce residual offset and 1/f noise. The inner chopper pair removes the 1/f noise, while the outer chopper pair reduces the residual offset. Our instrumentation amplifier using a nested chopping technique has residual offset under 100 nV. We also implement very low frequency filter. Since this filter needs very large RC time constant, we use a technique named 'diode connected PMOS' to increase R with small die area. The total power consumption is 3.1 mW at the supply voltage of 3.3V with the 0.35um general CMOS technology. The die area of implemented chip was
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