• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.7
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• pp.82-88
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• 1992

This paper presents one of the first comprehensive studies of how hot electron degradation impacts the input offset voltage of a CMOS differential amplifiers. This study utilizes the concept of a virtual source-coupled MOSFET pair in order to evaluate offset voltaged egradation directly from individual device measurement. Next, analytical models are developed to describe the offset voltage degradation. These models are used to examine how hot electron induced offset voltage is affected with the device parameters.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.3
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• pp.365-373
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• 2015

The performance of 4-switch 3-phase inverter(FSTPI) is mainly affected by the unbalanced voltages between two capacitors which replace two switches of conventional 6-switch 3-phase inverter(SSTPI). This paper proposes a DC offset current injection method to compensate the capacitor voltage unbalance for FSTPI. A simplified SVPWM method which can be applied to FSTPI is also proposed. The validity of the proposed methods is verified by computer simulation.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.12
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• pp.40-48
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• 1998

An offset compensation scheme for rail-to-rail CMOS op-amps with complementary input stages is presented. Two auxiliary amplifiers are used to compensate for the offsets of NMOS and PMOS differential input stages, and ping-pong control is employed for continuous-time operation. A 3V offset-compensated rail-to-rail CMOS op-amp has been designed and fabricated using a 0.8$\mu\textrm{m}$ single-poly, double-metal CMOS process. Measurement results show that offsets are reduced about 20 times by this scheme.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.1
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• pp.138-145
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• 1995

The offset voltage in silicon Hall plates is mainly caused by stress and strain in package, and by alignment in process. The offset voltage is appeared random for condition change with time in the factory, is non-linearly changed with temperature. In this paper proposed new method of design of Hall IC, and methematicaly proved relation layout of chip of 90$^{\circ}$-shift-current Hall plate pair is matched with "Differentail to single ended Conversion amplifier." In the experiment, the offset voltage is reduced about 1/100 time than the original offset voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.1-9
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• 2009

In this paper proposed a new method which adaptively eliminates comparator offsets using the threshold voltage shift by the Fowler-Nordheim stress. The method evaluates the sign of comparator offset and gives the FN stress to the stronger MOSFETs of the comparator, leading to offset reduction. We have used an appropriate stressing operation, named 'stress-packet', in order to converge the offset value to zero. We applied the method to the latch-type comparator which is prevalently used for DRAM bitline sense amplifier, and verified through experiments that offsets of the latch-type comparators are nearly eliminated with the stress-packet operations. We also discuss about the reliability issues that must be guaranteed for field application of this method.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.9
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• pp.13-19
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• 1999

This paper describes a design of an 8-bit 100KSPS 1mW CMOS A/D Converter. Using a novel systematic offset cancellation technique, we reduce the systematic offset voltage of operational amplifiers. Further, a new Gain amplifier is proposed. The proposed A/D Converter is fabricated with a $0.6{\mu}m$ single-poly triple-metal n-well CMOS technology. INL and DNL is within ${\pm}1LSB$, and SNR is about 43dB at the sampling frequency of 100KHz. The power consumption is $980{\mu}W$ at +3V power supply.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.1
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• pp.105-110
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• 2005

In this paper, a new technique to reduce the phase noise in microwave oscillators is proposed using the resonant characteristics of the Photonic Bandgap(PBG). We applied PBG structure to ground of the microstrip line resonator with the low Q(Quality factor). Therefore, we improved about 10 dBc in contrast to phase noise characteristic of the conventional microstrip line oscillator at 2.4 GHz ＠ 100 MHz offset. Output power is 7.09 dBm.

• Proceedings of the KIPE Conference
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• 2014.07a
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• pp.498-499
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• 2014

본 논문에서는 3상 PWM 옵셋전압방식을 응용하여 2상 인버터에 대한 PWM 제어방식을 확립하였다. 또한 기존의 3상 PWM 인버터 옵셋전압방식과의 최대 전압영역과 비교 분석하였다.

• Proceedings of the KIPE Conference
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• 2013.07a
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• pp.190-191
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• 2013

본 논문에서는 고역률 및 고효율 동작이 가능한 단일 전력단 forward-flyback 컨버터를 제안한다. 기존 단일전력단 forward 컨버터의 경우, 입력 전압이 출력 전압보다 낮은 경우 Dead zone 구간이 발생하여 고역률 획득이 어려우며, 자화 인덕터 offset 전류가 크기 때문에 자기소자의 손실로 인한 고효율 동작이 어렵다. 본 논문에서 제안하는 forward-flyback 컨버터는 2차 측에 삽입된 DC 블러킹 캐패시터에 의해 자화 인덕터의 offset 전류를 감소 할 수 있고, 입력 전압에 관계 없이 항상 출력 측으로 에너지를 전달 할 수 있으므로 고효율 및 고역률 획득에 유리하다. 또한 coupled inductor를 사용한 출력 인덕터에 의해 출력 다이오드에는 각 각 동일한 전류가 흐르며, 전압 스트레스를 감소시킬 수 있는 장점이 있다. 제안된 단일 전력단 forward-flyback 컨버터의 타당성을 검증을 위하여 45W급 LED 전원 공급장치의 시작품 제작을 통한 실험 결과를 제시한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37A no.10
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• pp.809-814
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• 2012

We propose an adaptive threshold detector algorithm for multi-level holographic data storage based on the expectation-maximization (EM) method. In this paper, the signal intensities that are passed through the four-level holographic channel are modeled as a four Gaussian mixture with unknown DC offsets and the threshold levels are estimated based on the maximum likelihood criterion. We compare the bit error rate (BER) performance of the proposed algorithm with the non-adaptive threshold detection algorithm for various levels of DC offset and misalignments. Our proposed algorithm shows consistently acceptable performance when the DC offset variance is fixed or the misalignments are lower than 20%. When the DC offset varies with each page, the BER of the proposed method is acceptable when the misalignments are lower than 10% and DC offset variance is 0.001.