• Smart Structures and Systems
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• v.12 no.1
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• pp.23-39
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• 2013

In this article, a smart multifunctional optical system-on-a-chip (SOC) sensor platform is presented and its application for fiber Bragg grating (FBG) sensor interrogation in optical sensor networks is investigated. The smart SOC sensor platform consists of a superluminescent diode as a broadband source, a tunable microelectromechanical system (MEMS) based Fabry-P$\acute{e}$rot filter, photodetectors, and an integrated microcontroller for data acquisition, processing, and communication. Integrated with a wireless sensor network (WSN) module in a compact package, a smart optical sensor node is developed. The smart multifunctional sensor platform has the capability of interrogating different types of optical fiber sensors, including Fabry-P$\acute{e}$rot sensors and Bragg grating sensors. As a case study, the smart optical sensor platform is demonstrated to interrogate multiplexed FBG strain sensors. A time domain signal processing method is used to obtain the Bragg wavelength shift of two FBG strain sensors through sweeping the MEMS tunable Fabry-P$\acute{e}$rot filter. A tuning range of 46 nm and a tuning speed of 10 Hz are achieved. The smart optical sensor platform will open doors to many applications that require high performance optical WSNs.

• ETRI Journal
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• v.31 no.5
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• pp.545-553
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• 2009

String matching is a fundamental element of an important category of modern packet processing applications which involve scanning the content flowing through a network for thousands of strings at the line rate. To keep pace with high network speeds, specialized hardware-based solutions are needed which should be efficient enough to maintain scalability in terms of speed and the number of strings. In this paper, a novel architecture based upon a recently proposed data structure called the Bloomier filter is proposed which can successfully support scalability. The Bloomier filter is a compact data structure for encoding arbitrary functions, and it supports approximate evaluation queries. By eliminating the Bloomier filter's false positives in a space efficient way, a simple yet powerful exact string matching architecture is proposed that can handle several thousand strings at high rates and is amenable to on-chip realization. The proposed scheme is implemented in reconfigurable hardware and we compare it with existing solutions. The results show that the proposed approach achieves better performance compared to other existing architectures measured in terms of throughput per logic cells per character as a metric.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.7 s.337
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• pp.57-62
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• 2005

This paper describes the design of a high performance microwave single pole double throw (SPDT) monolithic microwave integrated circuit switch using GaAs pHEMT process. The switch design proposes a novel coplanar waveguide (CPW) impedance transform network which results in the low insertion loss and high isolation by compensating for the FET parasitics to get the low on-resistance and low off-capacitance. The proposed switch has the measured isolation of better than 24 dB and insertion loss of less than 2.6 dB from 53 to 61 GHz. The chip is fabricated with the size of 2.2mm $\times$ 1.6 mm.

• Journal of Korea Multimedia Society
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• v.4 no.4
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• pp.349-355
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• 2001

In this paper, we newly propose a performance enhanced CSMA/CD MAC(Medium Access Control) protocol for the Ethernet which changes its operation mode dynamically according to the network status, not fixed it as one of p-persistent mode and non-persistent mode. Dynamic mode change occurs independently on each node, and uses the consecutive success count and the fail count of the frame transmission. The simulation result shows that the dynamic mode change maintains the enhanced network utilization and transmission delay characteristics. Also we show the implementation simplicity of our MAC protocol through its conceptual design using the Ethernet commercial chip as it stands.

• Proceedings of the KIEE Conference
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• 1999.07b
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• pp.583-585
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• 1999

This paper presents the controller of multiple DC motors using the network. This controller has been built with 16-bits one chip microprocessor (87C196CA) which includes the integrated CAN serial communication and position control for two motors. Since only one microprocessor is needed, the proposed controller is not only cost effective but also powerful. The system is composed of one main controller, trajectory planner, and the other sub controller, position controller. The main controller which has been built using Visual Basic programming on the Pentium PC, generates the trajectory and then transmits it to the sub controller. The trajectory transmitted from the PC will be processed by the sub controller. Two motors are controlled using the conventional position control, PID, to reach them the same target position but with different velocities at the same time. The communications between the main controller and sub controller is performed through the RS-232 or the CAN communication The CAN would be safer and faster than serial communication network since it has non-destructive bitwise arbitration specification. In this paper, we consider the CAN communications generally and then show the usefulness of the proposed controller by demonstrating position control of two DC motors.

• Journal of the Korea Society of Computer and Information
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• v.13 no.6
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• pp.195-201
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• 2008

We proposed that is suitable network environment and wire/wireless communication network, easy of implementation, security level preservation, scalable & reconfigurable to TCP/IP protocol architecture to implement suitable smart card MS-Serpent cryptographic algorithm for smart card by hardware base chip level that software base is not implement. Implemented MT-Serpent cryptosystem have 4,032 in gate counter and 406.2Mbps@2.44MHz in throughput. Implemented MS-Serpent cryptographic algorithm strengthens security vulnerability of TCP/IP protocol to do to rescue characteristic of smart card and though several kind of services are available and keep security about many user in wire/wireless environment, there is important purpose.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.589-591
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• 2009

본 논문에서 제안하고 있는 RT-WISN(Real Time-Wireless Image Sensor Network)는 과거의 무선이미지 전송 기술에 비해 적은 전력을 소모하고 빠른 전송이 가능하게 하는 기술이다. 제안된 RT-WISN은 IEEE802.15.4 표준을 따르고 있으며, 현재 본 연구실에서 개발하고 있는 UoC(Ubiquitous on Chip) 메모리 구조를 응용하여 사용하고 있다. 본 논문에서 제안하고 있는 RT-WISN은 전송하고자 하는 대상이 되는 영상정보의 움직임 변화를 영상 전송 임계값 값을 사용하여 데이터 전송 시기를 결정함으로써 기존의 시스템에 비해 노드의 에너지를 보다 효율적으로 관리할 수 있는 기법 이다. 또한 본 논문에서는 제안된 전용 프로세서를 사용하여 보다 넓은 대역폭에서 필요한 영상 데이터를 효율적으로 전송할 수 있어 전송 시간 제어에 보다 용이함을 제공 한다. 무선센서 네트워크에서 이런 점들은 각 노드들의 생존 시간을 향상하게 되고, 고속의 전송이 가능하게 하는 장점으로 작용하게 된다. 본 논문에서는 Peer-to-Peer 상에서 실제 설계된 메모리 구조를 사용하여 이미지를 무선으로 전송하고 그 전송 시간과 도달률을 측정하여 RT-WISN이 무선 센서 네트워크에서의 검출된 영상 정보의 전송에 적합함을 보인다.

• Proceedings of the Korea Information Processing Society Conference
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• 2008.11a
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• pp.806-809
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• 2008

온칩(on-chip) 캐쉬는 외부 메모리로의 접근을 감소시키는 중요한 역할을 한다. 본 연구에서는 내장형 시스템에 맞추어 설계된 2-레벨 캐쉬 메모리 구조를 제안하고자 한다. 레벨1(L1) 캐쉬의 구성으로 작은 크기, 직접사상(direct-mapped) 그리고 바로쓰기(write-through)를 채용한다. 대조적으로 레벨2(L2) 캐쉬는 일반적인 캐쉬 크기와 집합연관(Set-associativity) 그리고 나중쓰기(write-back) 정책을 채용한다. 결과적으로 L1캐쉬는 한 사이클 이내에 접근될 수 있고 L2캐쉬는 전체 캐쉬의 미스율(global miss rate)을 낮추는데 효과적이다. 두 캐쉬 계층간 바로쓰기(write-thorough) 정책에서 오는 빈번한 L2 캐쉬 접근으로 인한 에너지 소비를 줄이기 위해 본 연구에서는 One-way 접근 기법을 제안하였다. 본 연구에서 제안한 2-레벨 캐쉬 메모리 구조는 평균적으로 26%의 성능향상과 43%의 에너지 소비 그리고 77%의 에너지-지연 곱에서 이득을 보여주었다.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.3_4
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• pp.149-159
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• 2003

The need for information security increases interests on cipher algorithms recently. Especially, a large volume of data transmission over high-band communication network requires faster encryption and decryption techniques for real-time processing. It would be a good solution for this problem that we implement the cipher algorithm in forms of hardware circuits. Though some previous researches use this approach, they focus only on repeatedly executing the core part of the algorithm to minimize the hardware chip size, while most cipher algorithms are inherently parallel. In this paper, we propose a new design for the SEED block cipher algorithm developed by KISA (Korea Information Security Agency) in 1998 as Korean standard cipher algorithm. It exploits the parallelism of the algorithm basically and implements it in a pipelined fashion. We described the design in VHDL program and performed functional simulations on the program, and then found that it worked correctly. In addition, we synthesized it and verified that it could be implemented in a single FPGA chip, implying that the new design can be Practically used for the actual hardware implementation of a high-speed and high-performance cipher system.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.8
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• pp.883-890
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• 2015

As the semiconductor processing technology has been developing, multiple cores or NoC(network on chip) can be contained in recent chips. GALS(globally asychronous locally synchronous) clocking scheme that has multi-clock domains with different frequencies or phase differences is widely used to solve power consumption and clock skew in a large chip with a single clock. A synchronizer is needed to avoid a synchronization problem between sender and receiver in GALS. In this paper, the setup and hold time of DFF required to design the synchronizer are measured using 180nm CMOS processing parameters depending on temperature, supply voltage, and the size of inverter in DFF. The simulation results based on the bisection method in HSPICE show that the setup and hold time are proportional to temperature, however they are inversely proportional to supply voltage, and negative values are measured for the hold time.