• 제목/요약/키워드: negative bias

검색결과 452건 처리시간 0.034초

Offset 구조 Poly-Si TFT의 Negative Bias Stress 효과 (Negative Bias Stress Effect with Offset Structure in Poly-Si TFT's)

  • 이제혁;변문기;임동규;조봉희;김영호
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 1998년도 추계학술대회 논문집
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    • pp.141-144
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    • 1998
  • The electrical characteristics of poly-Si TFT's with offset structure by negative bias stress are systematically investigated as a function of offset length. The changes of electrical characteristics, V$\_$th/, off-current, on/off ratio, in the offset structured poly-Si TFT's are smaller than that of the conventional structured poly-Si TFT's under the stress condition (V$\_$ds/=20V, V$\_$gs/=-20V). It is found that the hot carrier effect by negative bias stress is suppressed by the offset structured poly-Si TFT's because the local electric field near the drain region is decreased by offset region.

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Decoupled Plasma Nitridation 공정 적용을 통한 Negative Bias Temperature Instability 특성 개선 (Improvement of Negative Bias Temperature Instability by Decoupled Plasma Nitridation Process)

  • 박호우;노용한
    • 한국전기전자재료학회논문지
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    • 제18권10호
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    • pp.883-890
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    • 2005
  • In this paper, the established model of NBTI (Negative Bias Temperature Instability) mechanism was reviewed. Based on this mechanism, then, the influence of nitrogen was discussed among other processes. A constant concentration of nitrogen exists inside $SiO_2$ in order to prevent boron from diffusing and to increase dielectric constant. It was shown that NBTI improvement was achieved by controlling nitrogen profile. It was supposed that the existence of low activation energy of Si-N bonds at $Si-SiO_2$ interface attributes the improvement by making hydrogen prevent interface traps. It was also shown that improvement of NBTI can be achieved by more effective control of nitrogen profile. It was supposed that the maximum control of nitrogen profile can be achieved by DPN (Decoupled Plasma Nitridation) process.

RF Bias Effect of ITO Thin Films Reactively Sputtered on PET Substrates at Room Temperature

  • Kim, Hyun-Hoo;Shin, Sung-Ho
    • Transactions on Electrical and Electronic Materials
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    • 제5권3호
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    • pp.122-125
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    • 2004
  • ITO films were deposited on polyethylene terephthalate substrate by a dc reactive magnetron sputtering using rf bias without substrate heater and post-deposition thermal treatment. The dependency of rf substrate bias on plasma sputter processing was investigated to control energetic particles and improve ITO film properties. The substrate was applied negative rf bias voltage from 0 to -80 V. The composition of indium, tin, and oxygen atoms is strongly depended on the rf substrate bias. Oxygen deficiency is the highest at rf bias of -20 V. The electrical and optical properties of ITO films also are dominated obviously by negative rf bias.

P-채널 다결정 실리콘 박막 트랜지스터의 Alternate Bias 스트레스 효과 (Effect of Alternate Bias Stress on p-channel poly-Si TFT`s)

  • 김영호;조봉희;강동헌;길상근;임석범;임동준
    • 한국전기전자재료학회논문지
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    • 제14권11호
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    • pp.869-873
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    • 2001
  • The effects of alternate bias stress on p-channel poly-Si TFT\`s has been systematically investigated. We alternately applied positive and negative bias stress on p-channel poly-Si TFT\`s, device Performance(V$\_$th/, g$\_$m/, leakage current, S-slope) are alternately appeared to be increasing and decreasing. It has been shown that device performance degrade under the negative bias stress while improve under the positive bias stress. This effects have been related to the hot carrier injection into the gate oxide rather than the generation of defect states within the poly-Si/SiO$_2$ interface under alternate bias stress.

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HFCVD 방법을 이용한 다이아몬드 박막 증착에서의 Bias 효과 (Bias effect for diamond films deposited by HFCVD method)

  • 권민철;박홍준;최병구
    • 한국진공학회지
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    • 제7권2호
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    • pp.94-103
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    • 1998
  • HFCVD(Hot Filament Chemical Vapor Deposition)방법을 이용한 다이아몬드의 핵 생성과 성장에 있어서, 인가한 직류 bias를 변수로 하여 핵생성 밀도와 증착율의 변화를 조 사하였다. 반응압력 20torr, 메탄농도 1.0%, Filament 온도 $2100^{\circ}C$ 그리고 Substrate 온도 $980^{\circ}C$에서 증착 단계를 핵생성기와 성장기로 구분하고 각 단계마다 bias의 방향과 크기를 다르게 인가하면서 다이아몬드 박막을 증착시켰다. Negative bias는 핵생성기에는 핵생성을 촉진시키지만 성장기에도 계속 인가하면 결정입자의 지속적인 성장을 방해하고 결정 구조를 비다이아몬드 성분으로 변화시키는 작용을 하여 박막의 morphology에 좋지 않은 영향을 주 었다. Positive bias는 핵생성기와 성장기에서 모두 $CH_4$의 분해를 촉진시킨 결과 증착율의 향상을 가져왔다. 따라서 다이아몬드 박막의 증착시 핵생성기에서는 negative bias를 인가하 고 성장기에는 positive bias를 인가하는 것이 핵생성 밀도와 증착율의 향상에 효과적인 것 으로 조사되었다.

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부스트 Negative Bias를 가지는 단상 SRM 컨버터 (Single Phase SRM Converter with Boost Negative Bias)

  • ;석승훈;이동희;안진우
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2008년도 제39회 하계학술대회
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    • pp.879-880
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    • 2008
  • At the high speed operation, the boost negative bias can reduce the negative torque and increase the dwell angle, so the output power and efficiency can be improved. In this paper, a novel power converter for single phase SRM with boost negative bias is proposed. A simple passive capacitor circuit is added in the front-end, which consists of three diodes and one capacitor. Based on this passive capacitor network, the two capacitors can be connected in series and parallel in different condition. In proposed converter, the phase winding of SRM obtains general dc-link voltage in excitation mode and the double dc-link voltage in demagnetization mode. The operation modes of the proposed converter are analyzed in detail. Some computer simulation and experimental results are done to verify the performance of proposed converter.

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ILP 프로세서를 위한 부정적 간섭을 감소시키는 동적 분기예상 기법 (An Dynamic Branch Prediction Scheme to Reduce Negative Interferences for ILP Processors)

  • 박홍준;조영일
    • 인터넷정보학회논문지
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    • 제2권1호
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    • pp.23-30
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    • 2001
  • ILP 프로세서는 고성능을 유지하기 위해 정확한 분기예상 방법을 요구한다. Two-Level 분기예상 방법은 높은 분기예상 정확성을 갖는 것으로 알려져 있다. 그러나, 한 분기 명령이 다른 분기 명령에 의해 갱신된 PHT 엔트리를 사용할 때 간섭이 발생하며, 간섭 중 부정적 간섭은 잘못된 예상(misprediction)을 유발하여 성능에 부정적 영향을 주게 된다. Agree분기예상 방법에서는 BTB에 bias 비트를 추가하여 부정적 간섭을 긍정적 간섭으로 변환하여 예상 정확도를 높였으나, bios 비트를 잘못 설정하는 경우에는 오히려 부정적 간섭이 증가하게 된다. 본 논문에서는 이러한 부정적 간섭을 감소시키는 새로운 동적 분기예상 방법을 제안한다. 제안한 분기예상 방법은 수행시간에 bias 비트를 동적으로 변경시키기 위해 BTB의 엔트리에 hit 비트를 추가하였다. 그 결과 부정적 간섭을 효과적으로 감소시켜 예상 정확도를 향상시켰다. 제안된 방법의 효율성을 보여주기 위해, SPEC92int 벤치마크를 사용하여 성능을 평가한 결과, 제안된 방법이 기존의 방법보다 성능이 우수함을 확인하였다.

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Light Effects on the Bias Stability of Transparent ZnO Thin Film Transistors

  • Shin, Jae-Heon;Lee, Ji-Su;Hwang, Chi-Sun;KoPark, Sang-Hee;Cheong, Woo-Seok;Ryu, Min-Ki;Byun, Chun-Won;Lee, Jeong-Ik;Chu, Hye-Yong
    • ETRI Journal
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    • 제31권1호
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    • pp.62-64
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    • 2009
  • We report on the bias stability characteristics of transparent ZnO thin film transistors (TFTs) under visible light illumination. The transfer curve shows virtually no change under positive gate bias stress with light illumination, while it shows dramatic negative shifts under negative gate bias stress. The major mechanism of the bias stability under visible illumination of our ZnO TFTs is thought to be the charge trapping of photo-generated holes at the gate insulator and/or insulator/channel interface.

단상 SRM의 운전 특성 개선을 위한 새로운 패시브 컨버터 (A Novel Passive Converter for Improving Drive Characteristics of a Single Phase SRM)

  • 이동희;;안진우
    • 전기학회논문지
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    • 제58권8호
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    • pp.1519-1525
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    • 2009
  • This paper presents a novel passive converter for single phase SRM. The proposed passive converter has additional passive power circuit which is consisted by three diodes and one capacitor in the front-end of conventional asymmetric converter to supply a high negative bias during demagnetization. The high negative bias can reduce the demagnetization time and negative torque from tail current in single phase SRM. So, It can extend positive torque region by the extended turn-off position. In this paper, the structure and operating modes of a novel passive converter are introduced with mathematical model. The proposed single phase SRM using passive converter is verified by the computer simulation and experimental results.

P-채널 poly-Si TFT's의 Alternate Bias 스트레스 효과 (Effect of Alternate Bias Stress on p-channel poly-Si TFT's)

  • 이제혁;변문기;임동규;정주용;이진민
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 1999년도 춘계학술대회 논문집
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    • pp.489-492
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    • 1999
  • The effects of alternate bias stress on p-channel poly-Si TPT's has been systematically investigated. It has been shown that the application of alternate bias stress affects device degradation for the negative bias stress as well as device improvement for the positive bias stress. This effects have been related to the hot carrier injection into the gate oxide rather than the generation of defect states within the poly-Si/SiO$_2$ under bias stress.

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