• Proceedings of the KIEE Conference
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• 2006.10a
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• pp.97-98
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• 2006

High current behaviors of extended drain n-type metal-oxide-semiconductor field effects transistor (EDNMOS) with double polarity source (DPS) for electrostatic discharge (ESD) protection are analyzed. Simulation based contour analyses reveal that combination of bipolar junction transistor operation and deep electron channeling induced by high electron injection gives rise to the second on-state. Therefore, the deep electron channel formation needs to be prevented in order to realize stable and robust ESD protection performance. Based on our analyses, general methodology to avoid the double snapback and to realize stable ESD protection is to be discussed.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.133-134
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• 2006

A simple doping method to fabricate a very thin channel body of the n-type fin field-effect-transistor (FinFET) with a 20 nm gate length by solid-phase-diffusion (SPD) process is presented. Using As-doped spin-on-glass as a diffusion source of arsenic and the rapid thermal annealing, the n-type source-drain extensions with a three-dimensional structure of the FinFET devices were doped. The junction properties of arsenic doped regions were investigated by using the $n^+$-p junction diodes which showed excellent electrical characteristics. Single channel and multi-channel n-type FinFET devices with a gate length of 20-100 nm was fabricated by As-SPD and revealed superior device scalability.

• Journal of IKEEE
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• v.25 no.3
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• pp.511-516
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• 2021

The electrical characteristics of AlGaN/GaN/HEMT and MOSHFETs with NiO were studied. The threshold voltage of NiO MOSHFET revealed positive shift of +1.03 V than the -3.79 V of HEMT and negative shift of -1.73 V for SiO₂ MOSHFET. Also, NiO MOSHFET showed better linearity in drain current corresponding to gate voltage and higher transconductance at positive gate voltage than the others. The response of gate pulse with base voltage of -5 V was different for both transistors as HEMT showed 20 % drain current decrease at the frequency range of 0.1 Hz~10 Hz and NiO MOSHFET decreased continuously above 10 Hz.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.355-358
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• 2004

In this work, N-LDMOSFET(Lateral Double diffused MOSFET) was designed and fabricated on SOI(Silicon-On-Insulator) substrate, for such applications as motor controllers and high voltage switches, fuel injection controller systems in automobile and SSR(Solid State Rexay)etc. The LDMOSFET was designed to overcome the floating body effects that appear in the conventional thick SOI MOS structure by adding p+ region in source region. Also, RESURF(Reduced SURface Field) structure was proposed in this work in order to reduce a large on-resistance of LDMOSFET when operated keeping high break down voltage. Breakdown voltage was 268v in off-state ($V_{GS}$=OV) at room temperature in $22{\mu}m$ drift length LDMOSFET. When 5V of $V_{GS}$ and 30V of $V_{DS}$ applied, the on resistance(Ron), the transcon ductance($G_m$) and the threshold voltage($V_T$) was 1.76k$\Omega$, 79.7uA/V and 1.85V respectively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.63-63
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• 2009

In this work, we demonstrate 800V 4H-SiC power DMOSFETs with several structural alterations to observe static DC characteristics, such as a threshold voltage ($V_{TH}$) and a figure of merit ($V_B^2/R_{SP,ON}$). To optimize the static DC characteristics, we consider four design parameters; (a) the doping concentration ($N_{CSL}$) of current spreading layer (CSL) beneath the p-base region, (b) the thickness of p-base ($t_{BASE}$), (c) the doping concentration ($N_J$) and width ($W_J$) of a JFET region, (d) the doping concentration ($N_{EPI}$) and thickness ($t_{EPI}$) of epi-layer. Design parameters are optimized using 2D numerical simulations and the 4H-SiC DMOSFET structure results in high figure of merit ($V_B^2/R_{SP,ON}$>~$340MW/cm^2$) for a power MOSFET in $V_B{\sim}1200V$ range.

• Journal of Satellite, Information and Communications
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• v.10 no.4
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• pp.1-5
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• 2015

The ESD(electrostatic discharge) protection performance of PPS(PMOS pass structure) embedded N-type silicon controlled rectifier(NSCR_PPS) device with different partial p-well(PPW) structure was discussed for high voltage I/O applications. A conventional NSCR_PPS standard device shows typical SCR-like characteristics with low on-resistance, low snapback holding voltage and low thermal breakdown voltage, which may cause latch-up problem during normal operation. However, our proposed NSCR_PPS devices with modified PPW_PGM(primary gate middle) and optimal CPS(counter pocket source) implant demonstrate the stable ESD protection performance with high latch-up immunity.

• Proceedings of the KIEE Conference
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• 1998.11c
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• pp.735-736
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• 1998

Reduction of hot carrier degradation in MOS devices has been one of the most serious concerns for MOS-ULSIs. In this paper, three types of LDD structure for suppression of hot carrier degradation, such as spacer-induced degradation and decrease of performance due to increase of series resistance will be investigated. LDD-nMOSFETs used in this study had three different drain structure. (1) conventional ${\underline{S}}urface$ type ${\underline{L}}DD$(SL), (2) ${\underline{B}}uried$ type ${\underline{L}}DD$(BL), (3) ${\underline{S}}urface$urface ${\underline{I}}mplantation$ type LDD(SI). As a result, the surface implantation type LDD structure showed that improved hot carrier lifetime to comparison with conventional surface and buried type LDD structure.

• Proceedings of the KIEE Conference
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• 1989.11a
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• pp.122-126
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• 1989

A composite polycide struoture consisting of refractory metal and noble metal silicide film on top of polysilicon bas been considered as a replacement for polysilicon as a gate electrode and Interconnect line in MOSFET integrated circuits. In this paper presents divice characteristics of NOS with $TiSi_2/n^+$polyoide and $CoSi_2/n^+$polycide gate. Also, evaporated Ti,Co films on polysilicon has been annealed by RTA and furnace annealing in $N_2$ abient at temperature of $400^{\circ}C-1000^{\circ}C$. The Ti-,Co-silioide formation is characterized by 4-point probe, silicide growth rate and Its reproductivity bas been examined by SEM.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.346-349
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• 2002

High Power and high dose ion implantation is essentially needed to make power MOSFET devices based on SiC wafers, because the diffusivities of the impurities such as Al, N, p, B in SiC crystal are very low. In addition, it is needed high temperature annealing for electrical activation of the implanted species. Due to the very high annealing temperature, the surface morphology after electrical activation annealing becomes very rough. We have found the different surface morphologies between implanted and unimplanted region. The unimplanted region showed smoother surface morphology It implies that the damage induced by high energy ion implantation affects the roughening mechanism. Some parts of Si-C bonding are broken in the damaged layer, s\ulcorner the surface migration and sublimation become easy. Therefore the macrostep formation will be promoted. N-type 4H-SiC wafers, which were Al ion implanted at acceleration energy ranged from 30kev to 360kev, were activated at 1600$^{\circ}C$ for 30min. The pre-activation annealing for damage relaxation was performed at 1100-1500$^{\circ}C$ for 30min. The surface morphologies of pre-activation annealed and activation annealed were characterized by atomic force microscopy(AFM).

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.8
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• pp.637-640
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• 2009

In this work, we demonstrate 800 V 4H-SiC power DMOSFETs with several structural alterations to obtain a low threshold voltage ($V_{TH}$) and a high figure of merit ($V_B\;^2/R_{SP,ON}$), To optimize the device performance, we consider four design parameters; (a) the doping concentration ($N_{CSL}$) of current spreading layer (CSL) beneath the p-base region, (b) the thickness of p-base ($t_{BASE}$), (c) the doping concentration ($N_J$) and width ($W_J$) of a JFET region, (d) the doping concentration ($N_{EPI}$) and thickness ($t_{EPI}$) of epi-layer. These parameters are optimized using 2D numerical simulation and the 4H-SiC DMOSFET structure results in a threshold voltage ($V_{TH}$) below $^{\sim}$3.8 V, and high figure of merit ($V_B\;^2/R_{SP,ON}$>$^{\sim}$200 $MW/cm^2$) for a power MOSFET in $V_B\;^{\sim}$800 V range.