• Nuclear Engineering and Technology
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• 제52권8호
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• pp.1764-1770
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• 2020

The present work was mainly concerned with studying the operation of RC-phase shift oscillator based on MOSFET type 2N6660 under the influence of different temperature levels ranging from room temperature (25 ℃) up-to135 ℃ and gamma-irradiation up-to 3.5 kGy. In this concern, both the static (I-V) characteristic curves of MOSFET devices and the output signal of the proposed oscillator were recorded under ascending levels of both temperature and gamma-irradiation. From which, it is clearly shown that the drain current was decreased from 0.22 A, measured at 25 ℃, down to 0.163 A, at 135 ℃. On the other hand, its value was increased up-to 0.49 A, whenever the device was exposed to gamma-rays dose of 3.5 kGy. Considering RC-phase shift oscillator, the oscillation frequency and output pk-pk voltage were decreased whenever MOSFET device exposed to gamma radiation by ratio 54.9 and 91%, respectively. While, whenever MOSFET device exposed to temperature the previously mentioned parameters were shown to be decreased by ratio 2.07 and 46.2%.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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• pp.99-100
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• 2006

Silicon-on-insulator(SOI) MOSFET with SiGe/Si heterostructure channel is an attractive device due to its potent use for relaxing several limits of CMOS scaling, as well as because of high electron and hole mobility and low power dissipation operation and compatibility with Si CMOS standard processing. SOI technology is known as a possible solution for the problems of premature drain breakdown, hot carrier effects, and threshold voltage roll-off issues in sub-deca nano-scale devices. For the forthcoming generations, the combination of SiGe heterostructures and SOI can be the optimum structure, so that we have developed SOI n-MOSFETs with SiGe/Si heterostructure channel grown by reduced pressure chemical vapor deposition. The SOI n-MOSFETs with a SiGe/Si heterostructure are presented and their DC characteristics are discussed in terms of device structure and fabrication technology.

• 전기전자학회논문지
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• 제26권3호
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• pp.333-340
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• 2022

고전압용 정전기 보호소자인 DDDNMOS(double diffused drain N-type MOSFET) 소자의 더블 스냅백 방지를 위한 최적의 이온주입 조건을 결정하기 위해 공정 및 소자 시뮬레이션이 수행되었다. HP-Well, N^- 드리프트 및 N⁺ 드레인 이온주입량의 변화가 더블 스냅백 및 애발란치 브레이크다운 전압에 미치는 영향을 고찰함으로써 더블 스냅백을 방지하여 정전기 보호 성능 개선할 수 있었다. HP-Well 영역보다는 N^- 드리프트 영역의 이온주입 농도를 최적으로 설계할 경우, 1차 on 상태에서 2차 on 상태로 전이하는 것을 막아주므로 비교적 양호한 정전기 보호 성능을 얻을 수 있었다. 또한 드리프트 이온주입 농도는 누설전류 및 애발란치 브레이크다운 전압에도 영향을 미치므로 동작전압이 30V보다 큰 공정기술에서는 DPS와 같은 새로운 구조를 적용하거나, 대안으로 여러 공정 변수들을 종합(colligation)하여 적용할 경우 향상된 정전기 보호 성능을 실현할 수 있을 것이다.

• 대한전자공학회논문지SD
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• 제38권2호
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• pp.9-9
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• 2001

Nano-scale의 게이트 길이를 가지는 MOSFET소자는 접합 깊이가 20∼30㎚정도로 매우 얕은 소스/드레인 확장 영역을 필요로 한다. 본 연구에서는 $As₂^ +$ 이온의 10keV이하의 낮은 에너지 이온 주입과 RTA(rapid thermal annealing)공정을 적용하여 20㎚이하의 얕은 접합 깊이와 1.O㏀/□ 이하의 낮은 면저항 값을 가지는 $n ^+$-p접합을 구현 하였다. 이렇게 형성된 $n^ +$-p 접합을 nano-scale MOSFET소자 제작에 적용 시켜서 70㎚의 게이트 길이를 가지는 NMOSFET을 제작하였다. 소스/드레인 확장 영역을 $As₂^ +$ 5keV의 이온 주입으로 형성한 100㎚의 게이트 길이를 가지는 NMOSFET의 경우, 60mV의 낮은 $V_ T$(문턱 전압감소) 와 87.2㎷의 DIBL (drain induced barrier lowering) 특성을 확인하였다. $10^20$$㎝^ -3$이상의 도핑 농도를 가진 abrupt한 20㎚급의 얕은 접합, 그리고 이러한 접합이 적용된 NMOSFET소자의 전기적 특성들은 As₂/sup +/의 낮은 에너지의 이온 주입 기술이 nano-scale NMOSFET소자 제작에 적용될 수 있다는 것을 제시한다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.73-74
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• 2007

We fabricated strained-SOI(sSOI) n-/p-MOSFETs and investigated the electron/hole mobility characteristics. The subthreshold characteristics of sSOI MOSFETs were similar to those of conventional SOI MOSFET. However, The electron mobility of sSOI nMOSFETs was larger than that of the conventional SOI nMOSFETs. These mobility enhancement effects are attributed to the subband modulation of silicon conduction band.

• 반도체디스플레이기술학회지
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• 제16권2호
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• pp.49-54
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• 2017

In this paper, recent researches on new and renewable energy have been conducted due to problems such as energy exhaustion and environmental pollution, and new researches on high efficiency and high speed switching are needed. Therefore, we compared the efficiency by using high speed switching devices instead of IGBT which can't be used in high speed switching. The experiment was performed theoretically by applying the same parameters of the high speed switching devices which are the Cool MOS of Infineon Co., SiC C3M of Cree, and GaN FET device of Transform, by implementing the DC-DC boost converter and measuring the actual efficiency for output power and frequency. As a result, the GaN FET showed good efficiency at all switching frequency and output power.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 춘계학술대회 논문집 디스플레이 광소자 분야
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• pp.187-190
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• 2000

We fabricated general photo diode, surface etched photo diode and floating gate MOSFET by CMOS process. In a design stage, we expect that surface etched photo diode will be improved as to photo sensitivity. However, because the surface of silicon was damaged in etching process, the surface etched diode had a high dark current as well as low photo current level. Finally, we examined the current-voltage properties for the floating gate MOSFET on n-well and confirmed that the device can be act as an efficient photo-sensor. The floating gate MOSFET was operated in parasitic bipolar transistor mode.

• E2M - 전기 전자와 첨단 소재
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• 제7권2호
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• pp.107-116
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• 1994

In the manufacturing of VLSI circuits, variations of device characteristics due to the slight differences in process parameters drastically aggravate the performances of fabricated devices. Therefore, it is very important to establish optimal process conditions in order to minimize deviations of device characteristics. In this paper, we used one-dimensional process simulator, SUPREM-II, and two dimensional device simulator, MINIMOS 4.0 in order to extract optimal process parameter which can minimize changes of the device characteristics caused by process parameter variation in the case of short channel nMOSFET and pMOSFET device. From this simulation, we have derived the dependence relations between process parameters and device characteristics. Here, we have suggested a method to extract process parameters from design trend curve(DTC) obtained by these dependence relations. And we have discussed short channel effects and device limitations by scaling down MOSFET dimensions.

• 대한전자공학회논문지
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• 제19권1호
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• pp.9-13
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• 1982

본실험에서는 N형 Si기판 내부에 P+소오스, 드레인 영역동 마련하고 게이트전극으로서는 PH₃ 를 첨가한 구조로서 Poly-Si gate MOSFET를 제작하여 이에 대한 잡음 특성에 관해 고찰하였다. 실험결과 게이트 면적이 일정하고 막두께가 비교적 두꺼울때는 W/L비 1이상에서는 잡음이 정감되는 경향으로 대체로 이론에 일치하지만 1이하에서는 막두께에 따른 변화는 완만하다는 것이 실증되었다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2000년도 제15차 학술회의논문집
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• pp.509-509
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• 2000

The circuit is designed for improving the relationship between input voltage and output current of the MOS transistor, which is square function. This circuit can be used instead of n-channel MOSFET at once. The circuit consists of MOSFET, which acts as a voltage receiver. The source of MOSFET is connected to current control part which consist of bipolar transistors. The exponential characteristic of bipolar transistor is used to solve the square function of MOSFET that base on concept of log and anti-log circuit. The experimental results of simulation are agreed with the implemented circuit.