• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.281-284
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• 2001

This paper describes an analog multi-phase delay-locked loop (DLL) to solve the harmonic lock problem using current-starved inverter and shunt-capacitor delay cell. The DLL can be used not only as an internal clock buffer of microprocessors and memory It's but also as a multi-phase clock generator for gigabit serial interfaces. The proposed circuit was simulated in a 0.25${\mu}{\textrm}{m}$ CMOS technology to solve harmonic lock problem and to realize fast lock-on time and low-jitter we verified time interval less than 40 ps as the simulation results.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.143-146
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• 2016

A new area-efficient multi-phase clock frequency multiplier is presented. The proposed fractional-ratio frequency multiplying DLL (FFMDLL) is implemented in a 65 nm CMOS process and occupies an active area of just $0.01mm^2$. The proposed FFMDLL provides 8-phase output clocks and achieves a frequency range of 0.6-1.0 GHz with programmable multiplication ratios of N/M, where N = 4, 5, 8, 10 and M = 1, 2, 3. It achieves an effective peak-to-peak jitter of 5 ps and dissipates 3.4 mW from a 1.0 V supply at 1 GHz.

• Journal of IKEEE
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• v.26 no.4
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• pp.714-721
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• 2022

A phase-locked loop (PLL)-based frequency synthesizer is proposed for a system on a chip (SoC) using multi-frequency clock signals. The proposed PLL-based frequency synthesizer consists of a charge pump PLL which is implemented by a phase frequency detector (PFD), a charge pump (CP), a loop filter, a voltage controlled oscillator (VCO), and a frequency divider, and an edge combiner. The PLL outputs a 12-phase clock by a VCO using six differential delay cells. The edge combiner synthesizes the frequency of the output clock through edge combining and frequency division of the 12-phase output clock of the PLL. The proposed PLL-based frequency synthesizer is designed using a 55-nm CMOS process with a 1.2-V supply voltage. It outputs three clocks with frequencies of 166 MHz, 83 MHz and 124.5MHz for a reference clock with a frequency of 20.75 MHz.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.11
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• pp.1695-1699
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• 2012

This paper is proposed all digital wide-range clock and data recovery circuit. The Proposed clock data recovery circuit is possible input data rate which is suggested is wide-range that extends from 100Mb/s to 3Gb/s and used an phase error detector which can use a way of over-sampling a data by using a 1/2-rate multi-phase clock and phase rotator which is regular size per $2{\pi}$/16 and can make a phase rotation. So it could make the phase rotating in range of input data rate. Also all circuit is designed as a digital which has a specificity against a noise. This circuit is designed to 0.13um CMOS process and verified simulation to spectre tool.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.95-98
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• 2012

This paper describes a multiphase delay-locked loop (DLL) that generates a 32-phase output clock over the operating frequency range of 40 MHz to 280 MHz. The matrix-based delay line is used for high resolution of 1-bit delay. A calibration scheme, which improves the linearity of a delay line, is achieved by calibrating the nonlinearity of the input stage of the matrix. The multi-phase DLL is fabricated by using 0.11-${\mu}m$ CMOS process with a 1.2 V supply. At the operating frequency of 125MHz, the measurement results shows that the DNL is less than +0.51/-0.12 LSB, and the measured peak-to-peak jitter of the multi-phase DLL is 30 ps with input peak-to-peak jitter of 12.9 ps. The area and power consumption of the implemented DLL are $480{\times}550{\mu}m^2$ and 9.6 mW at the supply voltage of 1.2 V, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.6
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• pp.594-600
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• 2015

A 1.25 GHz multi-phase phase-rotating PLL is proposed for oversampling CDR applications and implemented with a low power and small area. Eight equidistant clock phases are simultaneously adjusted by the phase interpolator inside the PLL. The phase interpolator uses only two complementary clocks from a VCO, but it can cover the whole range of phase from $0^{\circ}$ to $360^{\circ}$ with the help of a PFD timing controller. The output clock phases are digitally adjusted with the resolution of 25 ps and both INL and DNL are less than 0.44 LSB. The proposed PLL was implemented using a 110 nm CMOS technology. It consumes 3.36 mW from 1.2 V supply and occupies $0.047mm^2$. The $jitter_{rms}$ and $jitter_{pk-pk}$ of the output clock are 1.91 ps and 18 ps, respectively.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.259-262
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• 2012

This paper describes a delay-locked loop (DLL) that generates a 64-phase clock with the operating frequency of 125MHz. The proposed DLL use a $4{\times}8$ matrix-based delay line to improve the linearity of a delay line. The output clock with 64-phase is generated by using a CMOS multiplex and a inverted-based interpolator from 32-phase clock which is the output clock of the $4{\times}8$ matrix-based delay line. The circuit for an initial phase lock, which is independent on the duty cycle ratio of the input clock, is used to prevent from the harmonic lock of a DLL. The proposed DLL is designed using a $0.18-{\mu}m$ CMOS process with a 1.8 V supply. The simulated operating frequency range is 40 MHz to 200 MHz. At the operating frequency of a 125 MHz, the worst phase error and jitter of a 64-phase clock are +11/-12 ps and 6.58 ps, respectively.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.791-794
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• 2003

The increasing computational capability of processors is driving the need for high bandwidth links to communicate and store the information that is processed. Such links are often an important part of multi processor interconnection, processor-to-memory interfaces and Serial-network interfaces. This paper describes a 0.11-${\mu}{\textrm}{m}$ CMOS 4 Gbp s/pin 3-Level transceiver using RSL/(Rambus Signaling Logic) for high bandwidth. This system which uses a high-gain windowed integrating receiver with wide common-mode range which was designed in order to improve SNR when operating with the smaller input overdrive of 3-Level. For multi-gigabit/second application, the data rate is limited by Inter-Symbol Interference (ISI) caused by low pass effects of channel, process-limited on-chip clock frequency, and serial link distance. In order to detect the transmited 4Gbps/pin with 3-Level data sucessfully ,the receiver is designed using 3-stage sense amplifier. The proposed transceiver employes multi-level signaling (3-Level Pulse Amplitude Modulation) using clock multi phase, double data rate and Prbs patten generator. The transceiver shows data rate of 3.2 ~ 4.0 Gbps/pin with a 1GHz internal clock.

• The Journal of the Korea Contents Association
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• v.10 no.2
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• pp.72-80
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• 2010

The 1Gbps clock and data recovery (CDR) circuit using the proposed multi-point phase detector (PD) is presented. The proposed phase detector generates up/down signals comparing 3-point that is data transition point and clock rising/falling edge. The conventional PD uses the pulse width modulation (PWM) that controls the voltage controlled oscillator (VCO) using the width of a pulse period's multiple. However, the proposed PD uses the pulse number modulation (PNM) that regulates the VCO with the number of half clock cycle pulse. Therefore the proposed PD can controls VCO preciously and reduces the jitter. The CDR circuit is tested using 1Gbps $2^{31}-1$ pseudo random bit sequence (PRBS) input data. The designed CDR circuit shows that is capable of recovering clock and data at rates of 1Gbps. The recovered clock jitter is 7.36ps at 1GHz and the total power consumption is about 12mW. The proposed circuit is implemented using a 0.18um CMOS process under 1.8V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.23-30
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• 2005

This paper describes a DLL(delay locked loop)-based multi-clock generator having the lower active stand-by power as well as a fast relocking after re-activating the DLL. for low power and high speed VLSI chip. It enables a frequency multiplication using frequency multiplier scheme and produces output clocks with 50:50 duty-ratio regardless of the duty-ratio of system clock. Also, digital control scheme using DAC enables a fast relocking operation after exiting a standby-mode of the clock system which was obtained by storing analog locking information as digital codes in a register block. Also, for a clock multiplication, it has a feed-forward duty correction scheme using multiphase and phase mixing corrects a duty-error of system clock without requiring additional time. In this paper, the proposed DLL-based multi-clock generator can provides a synchronous clock to an external clock for I/O data communications and multiple clocks of slow and high speed operations for various IPs. The proposed DLL-based multi-clock generator was designed by the area of $1796{\mu}m\times654{\mu}m$ using $0.35-{\mu}m$ CMOS process and has $75MHz\~550MHz$ lock-range and maximum multiplication frequency of 800 MHz below 20psec static skew at 2.3v supply voltage.