• Title/Summary/Keyword: multi-level cell

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NAND Flash 메모리 저장 장치에서의 Error Control Code 응용

  • Lee, Gi-Jun;Lee, Myeong-Gyu;Sin, Beom-Gyu;Gong, Jun-Jin
    • Information and Communications Magazine
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    • v.32 no.6
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    • pp.16-22
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    • 2015
  • NAND flash 메모리의 집적도를 높이기 위한 주요 기술로, 데이터가 저장되는 cell 자체의 크기를 줄여주는 미세 공정화와 cell 당 저장되는 정보량을 늘려주는 멀티-레벨(multi-level)화가 사용되고 있다. 이러한 기술의 적용은 NAND flash 메모리 자체의 오류를 증가시키게 되므로, NAND flash 메모리 기반 데이터 저장 장치의 신뢰성을 높은 수준으로 유지하기 위해서는 우수한 정정 능력을 갖는 ECC(error control code) 를 사용하는 것이 필수적이다. 본고에서는 NAND flash 메모리의 신뢰성 특성과 함께 NAND flash 메모리를 사용하는 데이터 저장 장치에서의 ECC의 응용에 대해서 살펴보고자 한다.

Etchingless Fabrication of Bi-level Microstructures for Liquid Crystal Displays on Plastic Substrates

  • Hong, Jong-Ho;Cho, Seong-Min;Kim, Yeun-Tae;Lee, Sin-Doo
    • Journal of Information Display
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    • v.9 no.4
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    • pp.6-10
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    • 2008
  • In this study, the selective-wettability-inscription (SWI) technique for the wet-etchingless fabrication of surface microstructures applicable to wide-viewing liquid crystal displays (LCDs) on plastic substrates was demonstrated. On the basis of the selective wetting of the photopolymer, the bi-level microstructures were spontaneously formed to serve as spacers for maintaining uniform cell gap and protrusions for the generation of multi-domains. The LC cell that has bi-level microstructures shows good extinction in the field-off state and a wide-viewing property in the field-on state. The SWI technique would be useful for the fabrication of flexible displays on plastic substrates.

Spatio-temporal Load Forecasting Considering Aggregation Features of Electricity Cells and Uncertainties in Input Variables

  • Zhao, Teng;Zhang, Yan;Chen, Haibo
    • Journal of Electrical Engineering and Technology
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    • v.13 no.1
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    • pp.38-50
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    • 2018
  • Spatio-temporal load forecasting (STLF) is a foundation for building the prediction-based power map, which could be a useful tool for the visualization and tendency assessment of urban energy application. Constructing one point-forecasting model for each electricity cell in the geographic space is possible; however, it is unadvisable and insufficient, considering the aggregation features of electricity cells and uncertainties in input variables. This paper presents a new STLF method, with a data-driven framework consisting of 3 subroutines: multi-level clustering of cells considering their aggregation features, load regression for each category of cells based on SLS-SVRNs (sparse least squares support vector regression networks), and interval forecasting of spatio-temporal load with sampled blind number. Take some area in Pudong, Shanghai as the region of study. Results of multi-level clustering show that electricity cells in the same category are clustered in geographic space to some extent, which reveals the spatial aggregation feature of cells. For cellular load regression, a comparison has been made with 3 other forecasting methods, indicating the higher accuracy of the proposed method in point-forecasting of spatio-temporal load. Furthermore, results of interval load forecasting demonstrate that the proposed prediction-interval construction method can effectively convey the uncertainties in input variables.

An Efficient SLC Transition Method for Improving Defect Rate and Longer Lifetime on Flash Memory (플래시 메모리 상에서 불량률 개선 및 수명 연장을 위한 효율적인 단일 비트 셀 전환 기법)

  • Hyun-Seob Lee
    • Journal of Internet of Things and Convergence
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    • v.9 no.3
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    • pp.81-86
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    • 2023
  • SSD (solid state disk), which is flash memory-based storage device, has the advantages of high density and fast data processing. Therefore, it is being utilized as a storage device for high-capacity data storage systems that manage rapidly increasing big data. However, flash memory, a storage media, has a physical limitation that when the write/erase operation is repeated more than a certain number of times, the cells are worn out and can no longer be used. In this paper, we propose a method for converting defective multi-bit cells into single-bit cells to reduce the defect rate of flash memory and extend its lifetime. The proposed idea distinguishes the defects and treatment methods of multi-bit cells and single-bit cells, which have different physical characteristics but are treated as the same defect, and converts the expected defective multi-bit cells into single-bit cells to improve the defect rate and extend the overall lifetime. Finally, we demonstrate the effectiveness of our proposed idea by measuring the increased lifetime of SSD through simulations.

Analysis of Voltage Delay and Compensation for Current Control in H-Bridge Multi-Level Inverter (H-브릿지 멀티레벨 인버터의 전압 지연 해석 및 전류 제어 보상)

  • Park, Young-Min;Ryu, Han-Seong;Lee, Hyun-Won;Jung, Myung-Gil;Lee, Se-Hyun
    • The Transactions of the Korean Institute of Power Electronics
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    • v.15 no.1
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    • pp.43-51
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    • 2010
  • This paper proposes an analysis of voltage delay and compensation for current control in H-Bridge Multi-Level (HBML) inverters for a medium voltage motor drive with vector control. It is shown that the expansion and modularization capability of the HBML inverter is improved in case of using Phase-Shifted Pulse Width Modulation (PSPWM) since individual inverter modules operate more independently. But, the PSPWM of HBML has a phase difference between reference voltage and real voltage, which can cause instability in the current regulator at high speed where the ratio of the sampling frequency to the output frequency is insufficient. This instability of the current regulator is removed by adding a proposed method which compensate a phase difference between reference voltage and real voltage. The proposed method is suitable for HBML inverter controlled by PSPWM with low switching frequency and high speed motor drive. The validity of the proposed method is verified experimentally on 6,600[V] 1,400[kW] induction motor fed by an 13-level HBML inverter.

MLC NAND-type Flash Memory Built-In Self Test for research (MLC NAND-형 Flash Memory 내장 자체 테스트에 대한 연구)

  • Kim, Jin-Wan;Kim, Tae-Hwan;Chang, Hoon
    • Journal of the Institute of Electronics and Information Engineers
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    • v.51 no.3
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    • pp.61-71
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    • 2014
  • As the occupancy rate of the flash memory increases in the storage media market for the embedded system and the semi-conductor industry grows, the demand and supply of flash memory is increasing by a big margin. They are especially used in large quantity in the smart phones, tablets, PC, SSD and Soc(System on Chip) etc. The flash memory is divided into the NOR type and NAND type according to the cell arrangement structure and the NAND type is divided into the SLC(Single Level Cell) and MLC(Multi Level Cell) according to the number of bits that can be stored in each cell. Many tests have been performed on NOR type such as BIST(Bulit-In Self Test) and BIRA(Bulit-In Redundancy Analysis) etc, but there is little study on the NAND type. For the case of the existing BIST, the test can be proceeded using external equipments like ATE of high price. However, this paper is an attempt for the improvement of credibility and harvest rate of the system by proposing the BIST for the MLC NAND type flash memory of Finite State Machine structure on which the pattern test can be performed without external equipment since the necessary patterns are embedded in the interior and which uses the MLC NAND March(x) algorithm and pattern which had been proposed for the MLC NAND type flash memory.

Single-Cell Toolkits Opening a New Era for Cell Engineering

  • Lee, Sean;Kim, Jireh;Park, Jong-Eun
    • Molecules and Cells
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    • v.44 no.3
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    • pp.127-135
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    • 2021
  • Since the introduction of RNA sequencing (RNA-seq) as a high-throughput mRNA expression analysis tool, this procedure has been increasingly implemented to identify cell-level transcriptome changes in a myriad of model systems. However, early methods processed cell samples in bulk, and therefore the unique transcriptomic patterns of individual cells would be lost due to data averaging. Nonetheless, the recent and continuous development of new single-cell RNA sequencing (scRNA-seq) toolkits has enabled researchers to compare transcriptomes at a single-cell resolution, thus facilitating the analysis of individual cellular features and a deeper understanding of cellular functions. Nonetheless, the rapid evolution of high throughput single-cell "omics" tools has created the need for effective hypothesis verification strategies. Particularly, this issue could be addressed by coupling cell engineering techniques with single-cell sequencing. This approach has been successfully employed to gain further insights into disease pathogenesis and the dynamics of differentiation trajectories. Therefore, this review will discuss the current status of cell engineering toolkits and their contributions to single-cell and genome-wide data collection and analyses.

Operation Characteristic of Transless type Grid-connected Inverter using Multi-level Switching circuit (멀티레벨 스위칭 회로를 이용한 트렌스리스형 계통 연계 인버터의 동작 특성)

  • Kim, Ju-Yong;No, Kwae-Hyeop;Jung, Tae-Uk
    • Proceedings of the KIEE Conference
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    • 2008.07a
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    • pp.916-917
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    • 2008
  • In this paper, Switching damage of switches that is used to proposed power conversion system is reduced by soft switching way. dissipation by part resonance and my resonance stress for resonance of resonance circuit are decreased. Is acted by conversion system high effectiveness. Have following characteristic. Design snubber circuit that is used by switch protection in existent hard work rate Topology by resonant circuit for sogt switching, circuit structure was simple and control system is easy. Also, Can generate free output voltage by multi level Tuesday of output that use individuation Power Cell's Phase Shift PWM, and Low-end switching frequency the harmonic is few.

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Sub-channel Allocation Based on Multi-level Priority in OFDMA Systems

  • Lee, JongChan;Lee, MoonHo
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.7 no.8
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    • pp.1876-1889
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    • 2013
  • Packet-based mobile multimedia services for the Internet differ with respect to their resource requirements, performance objectives, and resource usage efficiencies. Nonetheless, each mobile terminal should support a variety of multimedia services, sometimes even simultaneously. This paper proposes a sub-channel allocation scheme based on multi-level priority for supporting mobile multimedia services in an Orthogonal Frequency Division Multiple Access (OFDMA) system. We attempt to optimize the system for satisfying the Quality of Service (QoS) requirements of users and maximize the capacity of the system at the same time. In order to achieve this goal, the proposed scheme considers the Signal-to-Interference-plus-Noise Ratio (SINR) of co-sub-channels in adjacent cells, the Signal-to-Noise Ratio (SNR) grade of each sub-channel in the local cell on a per-user basis, and the characteristics of the individual services before allocating sub-channels. We used a simulation to evaluate our scheme with the performance measure of the outage probabilities, delays, and throughput.

Evaluation of Multi-Level Memory Characteristics in Ge2Sb2Te5/TiN/W-Doped Ge2Sb2Te5 Cell Structure (Ge2Sb2Te5/TiN/W-Doped Ge2Sb2Te5 셀 구조의 다중준위 메모리 특성 평가 )

  • Jun-Hyeok Jo;Jun-Young Seo;Ju-Hee Lee;Ju-Yeong Park;Hyun-Yong Lee
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.37 no.1
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    • pp.88-93
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    • 2024
  • To evaluate the possibility as a multi-level memory medium for the Ge2Sb2Te5/TiN/W-doped Ge2Sb2Te5 cell structure, the crystallization rate and stabilization characteristics according to voltage (V)- and current (I)- pulse sweeping were investigated. In the cell structures prepared by a magnetron sputtering system on a p-type Si (100) substrate, the Ge2Sb2Te5 and W-doped Ge2Sb2Te5 thin films were separated by a barrier metal, TiN, and the individual thicknesses were varied, but the total thickness was fixed at 200 nm. All cell structures exhibited relatively stable multi-level states of high-middle-low resistance (HR-MR-LR), which guarantee the reliability of the multilevel phase-change random access memory (PRAM). The amorphousto-multilevel crystallization rate was evaluated from a graph of resistance (R) vs. pulse duration (T) obtained by the nanoscaled pulse sweeping at a fixed applied voltage (12 V). For all structures, the phase-change rates of HR→MR and MR→LR were estimated to be approximately t<20 ns and t<40 ns, respectively, and the states were relatively stable. We believe that the doublestack structure of an appropriate Ge-Sb-Te film separated by barrier metal (TiN) can be optimized for high-speed and stable multilevel PRAM.