• Journal of KIISE:Computer Systems and Theory
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• v.34 no.12
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• pp.618-629
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• 2007

In this paper, we propose an effective memory test environment, called a virtualized kernel, for 64bit multi-core computing environments. The term of effectiveness means that we can test all of the physical memory space, even the memory space occupied by the kernel itself, without rebooting. To obtain this capability, our virtualized kernel provides four mechanisms. The first is direct accessing to physical memory both in kernel and user mode, which allows applying various test patterns to any place of physical memory. The second is making kernel virtualized so that we can run two or more kernel image at the different location of physical memory. The third is isolating memory space used by different instances of virtualized kernel. The final is kernel hibernation, which enables the context switch between kernels. We have implemented the proposed virtualized kernel by modifying the latest Linux kernel 2.6.18 running on Intel Xeon system that has two 64bit dual-core CPUs with hyper-threading technology and 2GB main memory. Experimental results have shown that the two instances of virtualized kernel run at the different location of physical memory and the kernel hibernation works well as we have designed. As the results, the every place of physical memory can be tested without rebooting.

• Journal of the Semiconductor & Display Technology
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• v.8 no.1
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• pp.13-17
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• 2009

In PRAM applications, the devices can be made for both binary and multi-state storage. The ability to attain intermediate stages comes either from the fact that some chalcogenide materials can exist in configurations that range from completely amorphous to completely crystalline or from designing device structure such a way that mimics multiple phase chase phenomena in single cell. We have designed stack-structured phase change memory cell which operates as multi-state storage. Amorphous $Ge_xTe_{100-x}$ chalcogenide materials were stacked and a diffusion barrier was chosen for each stack layers. The device is operated by crystallizing each chalcogenide material as sequential manner from the bottom layer to the top layer. The amplitude of current pulse and the duration of pulse width was fixed and number of pulses were controlled to change overall resistance of the phase change memory cell. To optimize operational performance the thickness of each chalcogenide was controlled based on simulation results.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.6
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• pp.1040-1048
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• 1987

We propose a hardware architecture called Multiring which is applicable for various geometrical operations on rectilinear objects such as design rule checking in VLSI layout and many image processing operations including noise suppression and coutour extraction. It has both a fast execution speed and extremely high flexibility. The whole architecture is mainly divided into four parts` I/O between host and Multiring, ring memory, linear processor array and instruction decoder. Data transmission between host and Multiring is bit serial thereby reducing the bandwidth requirement for teh channel and the number of external pins, while each row data in the bit map stored in ring memory is processed in the corresponding processor in full parallelism. Each processor is simultaneously configured by the instruction decoder/controller to perform one of the 16 basic instructions such as Boolean (AND, OR, NOT, and Copy), geometrical(Expand and Shrink), and I/O operations each ring cycle, which gives Multiring maximal flexibility in terms of design rule change or the instruction set enhancement. Correct functional behavior of Multiring was confirmed by successfully running a software simulator having one-to-one structural correspondence to the Multiring hardware.

• Journal of Advanced Marine Engineering and Technology
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• v.35 no.6
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• pp.842-848
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• 2011

A fabricated hybrid control board using multi-communication is designed with a low power 8-bit microcontroller, ATxmega128A1. The microcontroller consists of 8 UART (Universal asynchronous receiver/transmitter) ports, 2 kbytes EEPROM, 128 kbytes flash memory, 8 kbytes SRAM. The 8 URAT ports are used for a multi-communication modem, a GPS module, etc. The EEPROM is used for saving a configuration for running programs, and the flash memory of 128 kbytes is used for storing a F/W (Firm Ware), and the 8 kbytes SRAM is used for stack and for storing memory of global variables while running programs. If we use the multi-communication of CDMA, TRS and RF to remotely control Aid to Navigation, it is able to remove the communication shadow area. Even though there is a shadow area for an individual communication method, we can select an optimal communication method. The compatibility of data has been enhanced as using of same data frame per communication device. For the test, 8640 of data have been collected from each buoy during 30 days in every 5 minutes and the receiving rate of the data has shown more than 85 %.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.9 no.4
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• pp.419-427
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• 2016

In this paper, a 64b small-area MTP memory IP is designed. A VPPL (=VPP/3) regulator and a VNN (=VNN/3) charge pump are removed since the inhibit voltages of an MTP memory cell are all 0V instead of the conventional voltages of VPP/3 and VNN/3. Also, a VPP charge pump is removed since the VPP program voltage is supplied from an external pad. Furthermore, a VNN charge pump is designed to provide its voltage of -VPP as a one-stage negative charge pump using the VPP voltage. The layout size of the designed 64b MTP memory IP with MagnaChip's $0.18{\mu}m$ BCD process is $377.585{\mu}m{\times}328.265{\mu}m$ (=0.124mm2). Its DC-DC converter related layout size is 76.4 percent smaller than its conventional counterpart.

• The Journal of the Acoustical Society of Korea
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• v.20 no.1
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• pp.56-61
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• 2001

This paper presents the real-time implementation of an AMR (Adaptive Multi Rate) vocoder which is included in the asynchronous International Mobile Telecommunication (IMT)-2000 mobile ASIC. The implemented AMR vocoder is a multi-rate coder with 8 modes operating at bit rates from 12.2kbps down to 4.75kbps. Not only the encoder and the decoder as basic functions of the vocoder are implemented, but VAD (Voice Activity Detection), SCR (Source Controlled Rate) operation and frame structuring blocks for the system interface are also implemented in this vocoder. The DSP for AMR vocoder implementation is a 16bit fixed-point DSP which is based on the TeakLite core and consists of memory block, serial interface block, register files for the parallel interface with CPU, and interrupt control logic. Through the implementation, we reduce the maximum operating complexity to 24MIPS by efficiently managing the memory structure. The AMR vocoder is verified throughout all the test vectors provided by 3GPP, and stable operation in the real-time testing board is also proved.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.12
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• pp.8-16
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• 2010

NAND multilevel cell (MLC) flash memory is widely issued because it can increase the capability of storage by storing two or more bits to a single cell. However if a number of levels in a cell increases, some physical features like cell to cell interference result cell voltage shift and it is known that a VT shift is unidirectional. To reduce errors by the effects, we can consider error correcting codes(ECC) or signal processing methods. We focus signal processing methods for the cell to cell interference voltage shift effects and propose the algorithms which reduce the effects of the voltage shift by estimating it and making level read voltages be adaptive. These new algorithms can be applied with ECC at the same time, therefore these algorithms are efficient for MLC error correcting ability. We show the bit error rate simulation results of the algorithms and compare the performance of the algorithms.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.3B
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• pp.339-348
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• 2004

Packet classification is an important factor to support various services such as QoS guarantee and VPN for users in Internet. Packet classification is a searching process for best matching rule on rule tables by employing multi-field such as source address, protocol, and port number as well as destination address in If header. In this paper, we propose hardware based packet classification algorithm by employing tree bitmap of multi-bit trio. We divided prefixes of searching fields and rule into multi-bit stride, and perform a rule searching with multi-bit of fixed size. The proposed scheme can reduce the access times taking for rule search by employing indexing key in a fixed size of upper bits of rule prefixes. We also employ a marker prefixes in order to remove backtracking during searching a rule. In this paper, we generate two dimensional random rule set of source address and destination address using routing tables provided by IPMA Project, and compare its memory usages and performance.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.6
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• pp.963-971
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• 1990

This paper proposes a memory intensive VLSI architecture for the realization of real-time 3x3 neighborhood processor based on the distributed arithmetic. The proposed architecture is characterized by a bit serial and multi-kernel parallel processing which exploits the pixel kernel parallelism and concurrency. The chip implements 8 neighborhood processing elements in parallel with efficirnt input and output modules which operate concurrently. Besides the a4chitectural design of a neighborhood processor, the design methodology using module generator concept has been considered and MOGOT(MOdule Generator Oriented VLSI design Tool) has been constructed based on the workstation. Based on these design environments MOGOT, it has been shown that the main part of the suggested architecture can be designed efficiently using 2\ulcorner double metal CMOS technology. It includes design of input delay and data conversion module, look-up table for inner product operation, carry save accumulator, output data converter and delay module, and control module.

• Proceedings of the IEEK Conference
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• 2001.06a
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• pp.269-272
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• 2001

Since Multi-way Search Tree reduces the number of the memory access by increasing the branch factor, it is considered a method to archive the high-speed IP address lookup. Using the combination of initial 16 bit may and Multi-way Search Tree, it also reduces the search time of If address lookup. Multi-way Search Tree consists of K keys and K＋1 key pointers. This paper shows how the E update of Multi-way Search Tree which consists of the one pointer within a node can be performed. Using the one pointer within a node, it increases the number of keys within a node and reduces the search time of IP lookup. We also describes IP updating methods such as modification, Insertion and Deletion of address entries. Our update scheme performs better than the method which rebuilds the entire IP routing table when IP update processes.