• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.7
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• pp.533-538
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• 2001

The barrier height is found to increase from 0.25 to 0.690 eV for Schottky contacts on n-InGaAs using deposition of Ag on a substrate cooled to 77K(LT). Surface analysis leads to an interface model for the LT diode in which there are oxide compounds of In:O and As:O between the metal and semiconductor, leading to behavior as a metal-insulator-semiconductor diode. The metal film deposited t LT has a finer and more uniform structure, as revealed by scanning electron microscopy and in situ metal layer resistance measurement. This increased uniformity is an additional reason for the barrier height improvement. In contrast, the diodes formed at room temperature exhibit poorer performance due to an unpassivated surface and non-uniform metal coverage on a microscopic level.

• 전기의세계
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• v.29 no.2
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• pp.111-117
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• 1980

Contacts formed by vacuum evaporation of As-Te-Si-Ge chalcogenide glass onto Al metal (99.9999%) are studied by measuring paralle capacitance C(V), Cp(w), resistance R(V), Rp(w), and I-V characteristics. The fact that contact metal alloying produced high-resistance region is confirmed from the measurements of parallel capacitance and resistance. From the I-V characteristics in the pre-switcing region, it is found that electronic conduction and sitching occurs in the vicinity of metal-amorphous semiconductor interface. From the experimental obsevations, it is concuded that the current flow in the thin film is space-charge limited current (SCLC) due to the tunneling of electrons through the energy barriers.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.2
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• pp.82-87
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• 2007

The electrical properties of metallic junction diodes and metallic source/drain (S/D) Schottky barrier metal-oxide-semiconductor field-effect transistor (SB-MOSFET) were simulated. By using the abrupt metallic junction at the S/D region, the short-channel effects in nano-scaled MOSFET devices can be effectively suppressed. Particularly, the effects of trap states at the metal-silicide/silicon interface of S/D junction were simulated by taking into account the tail distributions and the Gaussian distributions at the silicon band edge and at the silicon midgap, respectively. As a result of device simulation, the reduction of interfacial trap states with Gaussian distribution is more important than that of interfacial trap states with tail distribution for improving the metallic junction diodes and SB-MOSFET. It is that a forming gas annealing after silicide formation significantly improved the electrical properties of metallic junction devices.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.6
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• pp.648-654
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• 2003

Diamond MIS(Metal-Insulator-Semiconductor) diodes and MISFETs(Metal-Insulator-Semiconductor Field Effect Transistors) were fabricated by employing various fluorides as gate insulator, and their electrical properties were closely investigated by means of C-V measurements. The A1/BaF$_2$/diamond MIS structure exhibited outstanding electrical properties. The MIS diode showed a very low surface state density of ∼10$\^$10//$\textrm{cm}^2$ eV near the valence band edge, and the observed effective mobility(${\mu}$$\_$eff/) of the MISFET was 400 $\textrm{cm}^2$/Vs, which is the highest value obtained until now in the diamond FET. From the chemiphysical point of view, the above result might be explained by the reduction of adsorbed-oxygen on the diamond surface via strong chemical reaction by the constituent Ba atom in the insulator during the film deposition(Oxygen-Gettering Effect).

• Bulletin of the Korean Chemical Society
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• v.35 no.8
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• pp.2277-2280
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• 2014

The contact properties between gold and poly(3-hexylthiophene) (P3HT) films having either of two distinct molecular orientations and orderings were investigated. Thermal treatment increased the molecular ordering of P3HT and remarkably reduced the contact resistance at the electrode/semiconductor interface, which enhanced the electrical performance. This phenomenon was understood in terms of a small degree of metal penetration into the P3HT film as a result of the thermal treatment, which formed a sharp interface at the contact interface between the gold electrode and the organic semiconductor.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.530-537
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• 2013

An explicit surface potential calculation method of gate-all-around MOSFET (GAAMOSFET) devices which takes into account both interface trap charge and varying doping levels is presented. The results of the method are extensively verified by numerical simulation. Results from the model are used to find qualitative and quantitative effect of interface trap charge on subthreshold slope (SS) of GAAMOSFET devices. Further, design constraints of GAAMOSFET devices with emphasis on the effect of interface trap charge on device SS performance are investigated.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.5
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• pp.365-370
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• 2000

Schottky contacts on n-In$\_$0.53//Ga$\_$0.47//As have been made by metal deposition on substrates cooled to a temperature of 77K. The current-voltage and capacitance-voltage characteristics showed that the Schottky diodes formed at low temperature had a much improved barrier height compared to those formed at room temperature. The Schottky barrier height ø$\_$B/ was found to be increased from 0.2eV to 0.6eV with Ag metal. The saturation current density of the low temperature diode was about 4 orders smaller than for the room temperature diode. A current transport mechanism dominated by thermionic emission over the barrier for the low temperature diode was found from current-voltage-temperature measurement. Deep level transient spectroscopy studies exhibited a bulk electron trap at E$\_$c/-0.23eV. The low temperature process appears to reduce metal induced surface damage and may form an MIS (metal-insulator-semiconductor)-like structure at the interface.

• Transactions on Electrical and Electronic Materials
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• v.9 no.1
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• pp.6-11
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• 2008

In this study, we investigated effects of hydrogen annealing (HA) and plasma nitridation (PN) applied in order to improve $Si/SiO_2$ interface characteristics of TiN metal gate. In result, HA and PN showed a positive effect decreasing number of interface state $(N_{it})$ respectively. After FN stress for verifying reliability, however, we identified rapid increase of $N_{it}$ for TiN gate with HA, which is attributed to hydrogen related to a change of $Si/SiO_2$ interface characteristic. In contrast to HA, PN showed an improved Nit and gate oxide leakage characteristic due to several possible effects, such as blocking of Chlorine (Cl) diffusion and prevention of thermal reaction between TiN and $SiO_2$.

• Transactions on Electrical and Electronic Materials
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• v.18 no.6
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• pp.316-319
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• 2017

A new approach to improving the electrical characteristics and optical response of a polysilicon-based metal-semiconductor-metal (MSM) photodetector is proposed. To understand the cause of current restriction in the MSM photodetector, modified trap mechanisms are suggested, which include interfacial electron traps at the metal/polysilicon interface and silicon dangling bonds between silicon crystallite grains. Those traps were passivated using hydrogen ion implantation with subsequent post-annealing. Photodetectors that were ion-implanted under optima conditions exhibited improved photoconductivity and reduced dark current instability, implying that the hydrogen bonds in the polysilicon influence the simultaneous decreases in the density of dangling bonds at grain boundaries and the trapped positive charges at the contact interface.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.2
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• pp.69-76
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• 2005

Interface-trap density, lifetime and Schottky barrier height of erbium-silicided Schottky diode are evaluated using equivalent circuit method. The extracted interface trap density, lifetime and Schottky barrier height for hole are determined as $1.5{\times}10^{13} traps/cm^2$, 3.75 ms and 0.76 eV, respectively. The interface traps are efficiently cured by $N_2$ annealing. Based on the diode characteristics, various sizes of erbium- silicided/platinum-silicided n/p-type Schottky barrier metal-oxide-semiconductor field effect transistors (SB-MOSFETs) are manufactured from 20 m to 35nm. The manufactured SB-MOSFETs show excellent drain induced barrier lowering (DIBL) characteristics due to the existence of Schottky barrier between source and channel. DIBL and subthreshold swing characteristics are compatible with the ultimate scaling limit of double gate MOSFETs which shows the possible application of SB-MOSFETs in nanoscale regime.