• Korean Journal of Biological Psychiatry
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• v.12 no.2
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• pp.207-215
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• 2005

Objectives:This study was to compare verbal memory ability among patients with schizophrenia, bipolar manic patients and unipolar depressive patients, and to understand their charicteristics of memory process. Methods:All subjects were hospitalized patients and had been interviewed by using the Structured Clinical Interview for DSM-IV(SCID). Schizophrenic patients(N=40), bipolar manic patients(N=17), and unipolar depressive patients(N=20) were assessed with K-AVLT for verbal memory and with K-WAIS for verbal IQ. Three groups were compared regarding total immediate recall, delayed recall, delayed recognition, learning curve, memory retention, and retrieval efficiency under controlled verbal IQ. Multiple regression analysis was performed to find which clinical factors have an influence on verbal memory ability. Results:In MANCOVA, differences of verbal memory test scores among the groups were statistically significant(F=1.800, p<.05). In post hoc analysis, Patients with schizophrenia and bipolar mania showed poorer performance in immediate recall, delayed recall, delayed recognition, retrieval efficiency than unipolar depres- sive patients. And schizophrenics performed poorly in delayed recall, delayed recognition, retrieval efficiency than nonpsychotic affective disorder group, but no difference in total immediate recall, delayed recall, delayed recognition, retrieval efficiency between the schizophrenic group and the psychotic affective group. Conclusions:These results partially confirm previous reports of verbal memory ability among major psychiatric disorders. Our results showed that psychotic symptoms were related with verbal memory, and longer duration of illness was related with poorer performance in schizophrenia and unipolar depression.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.31-32
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• 2010

In our previous reports [1-3], electron transport for the switching and memory devices using alkyl thiol-tethered Ru-terpyridine complex compounds with metal-insulator-metal crossbar structure has been presented. On the other hand, among organic memory devices, a memory based on the OFET is attractive because of its nondestructive readout and single transistor applications. Several attempts at nonvolatile organic memories involve electrets, which are chargeable dielectrics. However, these devices still do not sufficiently satisfy the criteria demanded in order to compete with other types of memory devices, and the electrets are generally limited to polymer materials. Until now, there is no report on nonvolatile organic electrets using nano-interfaced organic monomer layer as a dielectric material even though the use of organic monomer materials become important for the development of molecularly interfaced memory and logic elements. Furthermore, to increase a retention time for the nonvolatile organic memory device as well as to understand an intrinsic memory property, a molecular design of the organic materials is also getting important issue. In this presentation, we report on the OFET memory device built on a silicon wafer and based on films of pentacene and a SiO2 gate insulator that are separated by organic molecules which act as a gate dielectric. We proposed push-pull organic molecules (PPOM) containing triarylamine asan electron donating group (EDG), thiophene as a spacer, and malononitrile as an electron withdrawing group (EWG). The PPOM were designed to control charge transport by differences of the dihedral angles induced by a steric hindrance effect of side chainswithin the molecules. Therefore, we expect that these PPOM with potential energy barrier can save the charges which are transported to the nano-interface between the semiconductor and organic molecules used as the dielectrics. Finally, we also expect that the charges can be contributed to the memory capacity of the memory OFET device.[4]

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.196-197
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• 2010

NAND형 charge trap flash (CTF) non-volatile memory (NVM) 소자가 30nm node 이하로 고집적화 되면서, 기존의 SONOS형 CTF NVM의 tunnel barrier로 쓰이는 SiO2는 direct tunneling과 stress induced leakage current (SILC)등의 효과로 인해 data retention의 감소 등 물리적인 한계에 이르렀다. 이에 따라 개선된 retention과 빠른 쓰기/지우기 속도를 만족시키기 위해서 tunnel barrier engineering (TBE)가 제안되었다. TBE NVM은 tunnel layer의 전위장벽을 엔지니어드함으로써 낮은 전압에서 전계의 민감도를 향상 시켜 동일한 두께의 단일 SiO2 터널베리어 보다 빠른 쓰기/지우기 속도를 확보할 수 있다. 또한 최근에 각광받는 high-k 물질을 TBE NVM에 적용시키는 연구가 활발히 진행 중이다. 본 연구에서는 Si3N4와 HfAlO (HfO2 : Al2O3 = 1:3)을 적층시켜 staggered의 새로운 구조의 tunnel barrier Capacitor를 제작하여 전기적 특성을 후속 열처리 온도와 방법에 따라 평가하였다. 실험은 n-type Si (100) wafer를 RCA 클리닝 실시한 후 Low pressure chemical vapor deposition (LPCVD)를 이용하여 Si3N4 3 nm 증착 후, Atomic layer deposition (ALD)를 이용하여 HfAlO를 3 nm 증착하였다. 게이트 전극은 e-beam evaporation을 이용하여 Al를 150 nm 증착하였다. 후속 열처리는 수소가 2% 함유된 질소 분위기에서 $300^{\circ}C$와 $450^{\circ}C$에서 Forming gas annealing (FGA) 실시하였고 질소 분위기에서 $600^{\circ}C{\sim}1000^{\circ}C$까지 Rapid thermal annealing (RTA)을 각각 실시하였다. 전기적 특성 분석은 후속 열처리 공정의 온도와 열처리 방법에 따라 Current-voltage와 Capacitance-voltage 특성을 조사하였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.5
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• pp.383-387
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• 2002

N-channel metal-ferroelectric-insulator-semiconductor field-effect-transistors (MFISFET's) by using $SrBi_2Ta_2O_9$/Silicon Nitride/Si (100) structure were fabricated. The fabricated devices exhibit comfortable memory windows, fast switching speeds, good fatigue resistances, and long retention times that are suitable for advanced ferroelectric memory applications. The estimated switching time and polarization ($2P_r$) of the fabricated FET measured at applied electric field of 376 kV/cm were less than 50 ns and about 1.5 uC/$\textrm{cm}^2$, respectively. The magnitude of on/off ratio indicating the stored information performance was maintained more than 3 orders until 3 days at room temperature. The $I_DV_G$ characteristics before and after being subjected to $10^11$ cycles of fatigue at a frequency of 1 MHz remained almost the same except a little distortion in off state.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.34-34
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• 2009

The electrical characteristics of tunnel barrier engineered charge trap flash (TBE-CTF) memory with $SiO_2/Si_3N_4/SiO_2/Si$ engineered tunnel barrier, $HfO_2$ charge trap layer and $Al_2O_3$ blocking oxide layer (MAHONOS) were investigated. The energy bad diagram was designed by using the quantum-mechanical tunnel model (QM) and then the CTF memory devices were fabricated. As a result, the best thickness combination of MAHONOS is confirmed. Moreover, not enhanced P/E speed (Program: about $10^6$ times) (Erase: about $10^4$ times) but also enhanced retention and endurance characteristics are represented.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.322-322
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• 2016

Phase change memory (PCM) has attracted much attention as one of the most promising candidates for next-generation nonvolatile memory. In that regard, the purposes of the study are to propose reference of effective pulse parameter to control phase switching operation and to invest the effect of nitrogen doped in PCM materials for improved cycling stability and economic energy consumption. Switching operation of PCM is affected by electric pulse parameter and as shown in figure.1 are composed to RT(rising time), ST(setting time), FT(falling time) and the effect of these parameter was precisely investigated. Transmission electron microscope (TEM) was used to confirm fine structure and retention cycle test was conducted to confirm reliability. Finally improvement reliability and economic power consumption in quantitatively are obtainable by optimum pulse parameter and nitrogen doping in GST material. these study is related to the engineering background of other semiconductor industries and it have confirmed to possibility further applications.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.12 no.3
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• pp.161-164
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• 2002

Polycrystalline and epitaxial heterostructure films of $La_{0.5}Sr_{0.5}CoO_{3}/Pb(Nb_{0.04}Zr_{0.28}Ti_{0.68})O_{3}/La_{0.5}Sr_{0.5}CoO_{3}$ (LSCO/PNZT/LSCO) capacitors were evaluated in terms of low voltage and high speed operation in high density memory, using TiN/Pt conducting barrier combination. Structural studies for a high density ferroelectric memory process flow, which requires the integration of conducting barrier layers to connect the drain of the pass-gate transistor to the bottom electrode of the ferroelectric stack, indicate complete phase purity (i.e. fully perovskite) in both epitaxial and polycrystalline materials. The polycrystalline capacitors show lower remnant polarization and coercive voltages. However, the retention, and high-speed characteristics are similar, indicating minimal influence of crystalline quality on the ferroelectric properties.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.189-190
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• 2008

The electrical characteristics of band-gap engineered tunneling barriers consisting of thin $SiO_2$ and $Si_3N_4$ dielectric layers were investigated. The band structure of stacked tunneling barriers was studied and the effectiveness of these tunneling barriers was compared with that of the conventional tunneling barrier. The band-gap engineered tunneling barriers show the lower operation voltage, faster speed and longer retention time than the conventional $SiO_2$ tunnel barrier. The thickness of each $SiO_2$ and $Si_3N_4$ layer was optimized to improve the performance of non-volatile memory.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.1
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• pp.7-11
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• 2009

In this study, p-channel silicon-oxide-nitride-oxide-silicon(SONOS) transistors are fabricated and characterized as an unit cell for NAND flash memory. The SONOS transistors are fabricated by $0.13{\mu}m$ low power standard logic process technology. The thicknesses of gate insulators are 2.0 nm for the tunnel oxide, 1.4 nm for the nitride layer, and 4.9 nm for the blocking oxide. The fabricated SONOS transistors show low programming voltage and fast erase speed. However, the retention and endurance of the devices show poor characteristics.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.101-101
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• 2007

We fabricated floating gate non-volatile memory devices with Si nanocrystals embedded in $SiN_x$ layer to achieve higher trap density. The average size of Si nanocrystals embedded in $SiN_x$ layer was ranging from 3 nm to 5 nm. The MOS capacitor and MOSFET devices with Si nanocrystals embedded in $SiN_x$ layer were analyzed the charging effects as a function of Si nanocrystals size.