• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.32 no.3
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• pp.201-206
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• 2019

This report constitutes the first demonstration in Korea of single-crystal lateral gallium oxide ($Ga_2O_3$) as a metal-oxide-semiconductor field-effect-transistor (MOSFET), with a breakdown voltage in excess of 480 V. A Si-doped channel layer was grown on a Fe-doped semi-insulating ${\beta}-Ga_2O_3$ (010) substrate by molecular beam epitaxy. The single-crystal substrate was grown by the edge-defined film-fed growth method and wafered to a size of $10{\times}15mm^2$. Although we fabricated several types of power devices using the same process, we only report the characterization of a finger-type MOSFET with a gate length ($L_g$) of $2{\mu}m$ and a gate-drain spacing ($L_{gd}$) of $5{\mu}m$. The MOSFET showed a favorable drain current modulation according to the gate voltage swing. A complete drain current pinch-off feature was also obtained for $V_{gs}<-6V$, and the three-terminal off-state breakdown voltage was over 482 V in a $L_{gd}=5{\mu}m$ device measured in Fluorinert ambient at $V_{gs}=-10V$. A low drain leakage current of 4.7 nA at the off-state led to a high on/off drain current ratio of approximately $5.3{\times}10^5$. These device characteristics indicate the promising potential of $Ga_2O_3$-based electrical devices for next-generation high-power device applications, such as electrical autonomous vehicles, railroads, photovoltaics, renewable energy, and industry.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.5
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• pp.25-33
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• 2011

This work proposes a skinny-type 10b 50MS/s 0.13um CMOS three-step pipeline ADC for CIS applications. Analog circuits for CIS applications commonly employ a high supply voltage to acquire a sufficiently acceptable dynamic range, while digital circuits use a low supply voltage to minimize power consumption. The proposed ADC converts analog signals in a wide-swing range to low voltage-based digital data using both of the two supply voltages. An op-amp sharing technique employed in residue amplifiers properly controls currents depending on the amplification mode of each pipeline stage, optimizes the performance of op-amps, and improves the power efficiency. In three FLASH ADCs, the number of input stages are reduced in half by the interpolation technique while each comparator consists of only a latch with low kick-back noise based on pull-down switches to separate the input nodes and output nodes. Reference circuits achieve a required settling time only with on-chip low-power drivers and digital correction logic has two kinds of level shifter depending on signal-voltage levels to be processed. The prototype ADC in a 0.13um CMOS to support 0.35um thick-gate-oxide transistors demonstrates the measured DNL and INL within 0.42LSB and 1.19LSB, respectively. The ADC shows a maximum SNDR of 55.4dB and a maximum SFDR of 68.7dB at 50MS/s, respectively. The ADC with an active die area of 0.53$mm^2$ consumes 15.6mW at 50MS/s with an analog voltage of 2.0V and two digital voltages of 2.8V ($=D_H$) and 1.2V ($=D_L$).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.3 s.357
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• pp.26-34
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• 2007

This Paper describes a chip design technique for body composition analyzer based on the BIA (Bioelectrical Impedance Analysis) method. All the functions of signal forcing circuits to the body, signal detecting circuits from the body, Micom, SRAM and EEPROMS are integrated in one chip. Especially, multi-frequency detecting method can be applied with selective band pass filter (BPF), which is designed in weak inversion region for low power consumption. In addition new full wave rectifier (FWR) is also proposed with differential difference amplifier (DDA) for high performance (small die area low power consumption, rail-to-rail output swing). The prototype chip is implemented with 0.35um CMOS technology and shows the power dissipation of 6 mW at the supply voltage of 3.3V. The die area of prototype chip is $5mm\times5mm$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.2
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• pp.61-67
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• 2006

We fabricate local damascene FinFET cell array in sub-60nm feature sized DRAM. The local damascene structure can remove passing-gate-effects in FinFET cell array. p+ boron in-situ doped polysilicon is chosen for the gate material, and we obtain a uniform distribution of threshold voltages at around 0.7V. Sub-threshold swing of 75mV/d and extrapolated off-state leakage current of 0.03fA are obtained, which are much suppressed values against those of recessed channel array transistors. We also obtain a few times higher on-state current. Based on the improved on- and off-state current characteristics, we expect that the FinFET cell array could be a new mainstream structure in sub-60nm DRAM devices, satisfying high density, low power, and high-speed device requirements.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.7
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• pp.659-664
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• 2016

In this paper, we suggest operational trans-conductance amplifier(OTA) for current-mode FIR filter that can be used in a digital circuit system requiring high operating frequency and low power consumption. The current-mode signal processing is one of the very innovative design method for a low power consumption system with high operating frequency because it shows a constant power regardless of frequency. From the simulation result using 0.35um CMOS process, when Vdd is 2V, it is confirmed that the proposed circuit showed the dynamic range of the about 1V, about 50% of supply voltage and output current swing of about 0~200uA. Also, the power consumption was evaluated with about 21uW and the active size for an integration was measured with $71um{\times}166um$.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.334-334
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• 2012

Transparent oxide semiconductors have recently attracted much attention as channel layer materials due to advantageous electrical and optical characteristics such as high mobility, high stability, and good transparency. In addition, transparent oxide semiconductor can be fabricated at low temperature with a low production cost and it permits highly uniform devices such as large area displays. A variety of thin film transistors (TFTs) have been studied including ZnO, InZnO, and InGaZnO as the channel layer. Recently, there are many studies for substitution of Ga in InGaZnO TFTs due to their problem, such as stability of devices. In this work, new quaternary compound materials, tantalum-indium-tin oxide (TaInSnO) thin films were fabricated by using co-sputtering and used for the active channel layer in thin film transistors (TFTs). We deposited TaInSnO films in a mixed gas (O2+Ar) atmosphere by co-sputtering from Ta and ITO targets, respectively. The electric characteristics of TaInSnO TFTs and thin films were investigated according to the RF power applied to the $Ta_2O_5$ target. The addition of Ta elements could suppress the formation of oxygen vacancies because of the stronger oxidation tendency of Ta relative to that of In or Sn. Therefore the free carrier density decreased with increasing RF power of $Ta_2O_5$ in TaInSnO thin film. The optimized characteristics of TaInSnO TFT showed an on/off current ratio of $1.4{\times}108$, a threshold voltage of 2.91 V, a field-effect mobility of 2.37 cm2/Vs, and a subthreshold swing of 0.48 V/dec.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.666-672
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• 2014

We have investigated the gate insulator effects on the electrical performance of p-type tin monoxide (SnO) thin-film transistors (TFTs). Various SnO TFTs are fabricated with different gate insulators of a thermal $SiO_2$, a plasma-enhanced chemical vapor deposition (PECVD) $SiO_x$, a $150^{\circ}C$-deposited PEVCD $SiO_x$, and a $300^{\circ}C$-deposited PECVD $SiO_x$. Among the devices, the one with the $150^{\circ}C$-deposited PEVCD $SiO_x$ exhibits the best electrical performance including a high field-effect mobility ($=4.86cm^2/Vs$), a small subthreshold swing (=0.7 V/decade), and a turn-on voltage around 0 (V). Based on the X-ray diffraction data and the localized-trap-states model, the reduced carrier concentration and the increased carrier mobility due to the small grain size of the SnO thin-film are considered as possible mechanisms, resulting in its high electrical performance.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.1
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• pp.110-116
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• 2016

This paper describes 1.2-V 5-Gb/s scalable low voltage signaling(SLVS) differential transmitter(TX) with a digital impedance calibration and equalizer. The proposed transmitter consists of a phase-locked loop(PLL) with 4-phase output clock, a 4-to-1 serializer, a regulator, an output driver, and an equalizer driver for improvement of the signal integrity. A pseudo random bit sequence generator is implemented for a built-in self-test. The proposed SLVS transmitter provides the output differential swing level from 80mV to 500mV. The proposed SLVS transmitter is implemented by using a 65-nm CMOS with a 1.2-V supply. The measured peak-to-peak time jitter of the implemented SLVS TX is about 46.67 ps at the data rate of 5Gb/s. Its power consumption is 1.88 mW/Gb/s.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.1
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• pp.22-29
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• 2006

We demonstrate highly manufacturable Multi-channel Field Effect Transistor (McFET) on bulk Si wafer. McFET shows excellent transistor characteristics, such as $5{\sim}6 times higher drive current than planar MOSFET, ideal subthreshold swing, low drain induced barrier lowering (DIBL) without pocket implantation and negligible body bias dependency, maintaining the same source/drain resistance as that of a planar transistor due to the unique feature of McFET. And suitable threshold voltage ($V_T$) for SRAM operation and high static noise margin (SNM) are achieved by using TiN metal gate electrode.

• ETRI Journal
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• v.37 no.6
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• pp.1135-1142
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• 2015

Multilayered ZnO-$SnO_2$ heterostructure thin films consisting of ZnO and $SnO_2$ layers are produced by alternating the pulsed laser ablation of ZnO and $SnO_2$ targets, and their structural and field-effect electronic transport properties are investigated as a function of the thickness of the ZnO and $SnO_2$ layers. The performance parameters of amorphous multilayered ZnO-$SnO_2$ heterostructure thin-film transistors (TFTs) are highly dependent on the thickness of the ZnO and $SnO_2$ layers. A highest electron mobility of $43cm^2/V{\cdot}s$, a low subthreshold swing of a 0.22 V/dec, a threshold voltage of 1 V, and a high drain current on-to-off ratio of $10^{10}$ are obtained for the amorphous multilayered ZnO(1.5nm)-$SnO_2$(1.5 nm) heterostructure TFTs, which is adequate for the operation of next-generation microelectronic devices. These results are presumed to be due to the unique electronic structure of amorphous multilayered ZnO-$SnO_2$ heterostructure film consisting of ZnO, $SnO_2$, and ZnO-$SnO_2$ interface layers.