JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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Fabrication and Electrical Properties of Local Damascene FinFET Cell Array in Sub-60nm Feature Sized DRAM

  • Kim, Yong-Sung (Korea Research Institue of Standard and Science) ;
  • Shin, Soo-Ho (Advanced Technology Development, Semiconductor R&D Center, Samsung Electronics Co., Ltd.) ;
  • Han, Sung-Hee (Advanced Technology Development, Semiconductor R&D Center, Samsung Electronics Co., Ltd.) ;
  • Yang, Seung-Chul (Advanced Technology Development, Semiconductor R&D Center, Samsung Electronics Co., Ltd.) ;
  • Sung, Joon-Ho (Advanced Technology Development, Semiconductor R&D Center, Samsung Electronics Co., Ltd.) ;
  • Lee, Dong-Jun (Advanced Technology Development, Semiconductor R&D Center, Samsung Electronics Co., Ltd.) ;
  • Lee, Jin-Woo (Advanced Technology Development, Semiconductor R&D Center, Samsung Electronics Co., Ltd.) ;
  • Chung, Tae-Young (Advanced Technology Development, Semiconductor R&D Center, Samsung Electronics Co., Ltd.)
  • Published : 2006.06.30
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Abstract

We fabricate local damascene FinFET cell array in sub-60nm feature sized DRAM. The local damascene structure can remove passing-gate-effects in FinFET cell array. p+ boron in-situ doped polysilicon is chosen for the gate material, and we obtain a uniform distribution of threshold voltages at around 0.7V. Sub-threshold swing of 75mV/d and extrapolated off-state leakage current of 0.03fA are obtained, which are much suppressed values against those of recessed channel array transistors. We also obtain a few times higher on-state current. Based on the improved on- and off-state current characteristics, we expect that the FinFET cell array could be a new mainstream structure in sub-60nm DRAM devices, satisfying high density, low power, and high-speed device requirements.

Keywords

References

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