• Title/Summary/Keyword: local damascene

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Fabrication and Electrical Properties of Local Damascene FinFET Cell Array in Sub-60nm Feature Sized DRAM

  • Kim, Yong-Sung;Shin, Soo-Ho;Han, Sung-Hee;Yang, Seung-Chul;Sung, Joon-Ho;Lee, Dong-Jun;Lee, Jin-Woo;Chung, Tae-Young
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.6 no.2
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    • pp.61-67
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    • 2006
  • We fabricate local damascene FinFET cell array in sub-60nm feature sized DRAM. The local damascene structure can remove passing-gate-effects in FinFET cell array. p+ boron in-situ doped polysilicon is chosen for the gate material, and we obtain a uniform distribution of threshold voltages at around 0.7V. Sub-threshold swing of 75mV/d and extrapolated off-state leakage current of 0.03fA are obtained, which are much suppressed values against those of recessed channel array transistors. We also obtain a few times higher on-state current. Based on the improved on- and off-state current characteristics, we expect that the FinFET cell array could be a new mainstream structure in sub-60nm DRAM devices, satisfying high density, low power, and high-speed device requirements.

A Study on the Optimized Copper Electrochemical Plating in Dual Damascene Process

  • Yoo, Hae-Young;Chang, Eui-Goo;Kim, Nam-Hoon
    • Transactions on Electrical and Electronic Materials
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    • v.6 no.5
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    • pp.225-228
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    • 2005
  • In this work, we studied the optimized copper thickness in Cu ECP (Electrochemical Plating). In order to select an optimized Cu ECP thickness, we examined Cu ECP bulge (bump, hump or over-plating amount), Cu CMP dishing and electrical properties of via hole and line trench over dual damascene patterned wafers split into different ECP Cu thickness. In the aspect of bump and dishing, the bulge increased according as target plating thickness decreased. Dishing of edge was larger than center of wafer. Also in case of electrical property, metal line resistance distribution became broad gradually according as Cu ECP thickness decreased. In conclusion, at least $20\%$ reduced Cu ECP thickness from current baseline; $0.8\;{\mu}m$ and $1.0\;{\mu}m$ are suitable to be adopted as newly optimized Cu ECP thickness for local and intermediate layer.

Electrodeposition for the Fabrication of Copper Interconnection in Semiconductor Devices (반도체 소자용 구리 배선 형성을 위한 전해 도금)

  • Kim, Myung Jun;Kim, Jae Jeong
    • Korean Chemical Engineering Research
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    • v.52 no.1
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    • pp.26-39
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    • 2014
  • Cu interconnection in electronic devices is fabricated via damascene process including Cu electrodeposition. In this review, Cu electrodeposition and superfilling for fabricating Cu interconnection are introduced. Superfilling results from the influences of organic additives in the electrolyte for Cu electrodeposition, and this is enabled by the local enhancement of Cu electrodeposition at the bottom of filling feature formed on the wafer through manipulating the surface coverage of organic additives. The dimension of metal interconnection has been constantly reduced to increase the integrity of electronic devices, and the width of interconnection reaches the range of few tens of nanometer. This size reduction raises the issues, which are the deterioration of electrical property and the reliability of Cu interconnection, and the difficulty of Cu superfilling. The various researches on the development of organic additives for the modification of Cu microstructure, the application of pulse and pulse-reverse electrodeposition, Cu-based alloy superfilling for improvement of reliability, and the enhancement of superfilling phenomenon to overcome the current problems are addressed in this review.

An Investigation of the Current Squeezing Effect through Measurement and Calculation of the Approach Curve in Scanning Ion Conductivity Microscopy (Scanning Ion Conductivity Microscopy의 Approach Curve에 대한 측정 및 계산을 통한 Current Squeezing 효과의 고찰)

  • Young-Seo Kim;Young-Jun Cho;Han-Kyun Shin;Hyun Park;Jung Han Kim;Hyo-Jong Lee
    • Journal of the Microelectronics and Packaging Society
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    • v.31 no.2
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    • pp.54-62
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    • 2024
  • SICM (Scanning Ion Conductivity Microscopy) is a technique for measuring surface topography in an environment where electrochemical reactions occur, by detecting changes in ion conductivity as a nanopipette tip approaches the sample. This study includes an investigation of the current response curve, known as the approach curve, according to the distance between the tip and the sample. First, a simulation analysis was conducted on the approach curves. Based on the simulation results, then, several measuring experiments were conducted concurrently to analyze the difference between the simulated and measured approach curves. The simulation analysis confirms that the current squeezing effect occurs as the distance between the tip and the sample approaches half the inner radius of the tip. However, through the calculations, the decrease in current density due to the simple reduction in ion channels was found to be much smaller compared to the current squeezing effect measured through actual experiments. This suggests that ion conductivity in nano-scale narrow channels does not simply follow the Nernst-Einstein relationship based on the diffusion coefficients, but also takes into account the fluidic hydrodynamic resistance at the interface created by the tip and the sample. It is expected that SICM can be combined with SECM (Scanning Electrochemical Microscopy) to overcome the limitations of SECM through consecutive measurement of the two techniques, thereby to strengthen the analysis of electrochemical surface reactivity. This could potentially provide groundbreaking help in understanding the local catalytic reactions in electroless plating and the behaviors of organic additives in electroplating for various kinds of patterns used in semiconductor damascene processes and packaging processes.