• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.4
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• pp.251-265
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• 2001

As the device scaling proceeds, the operating voltage(VDD) of giga-bit DRAMs is expected to be reduced to 1.5V or down, fir improving the device reliability and reducing the power dissipation. Therefore the low-voltage circuit design techniques are required to implement giga-bit DRAMs. In this work, state-of-art low-voltage DRAM circuit techniques are reviewed, and four kinds of low-voltage circuit design techniques are newly proposed for giga-bit DRAMs. Measurement results of test chips and SPICE simulation results are presented for the newly proposed circuit design techniques, which include a hierarchical negative-voltage word-line driver with reduced subthreshold leakage current, a two-phase VBB(Back-Bias Voltage) generator, a two-phase VPP(Boosted Voltage) generator and a bandgap reference voltage generator.

• Journal of the Korea Society of Computer and Information
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• v.24 no.11
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• pp.1-9
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• 2019

In this paper, we propose a Small Active Command scheme which reduces the power consumption of the command bus to DRAM. To do this, we target the ACTIVE command, which consists of multiple packets, containing the row address that occupies the largest size among the addresses delivered to the DRAM. The proposed scheme identifies frequently referenced row addresses as Hot pages first, and delivers index numbers of small caches (tables) located in the memory controller and DRAM. I-ACTIVE and I-PRECHARGE commands using unused bits of existing DRAM commands are added for index number transfer and cache synchronization management. Experimental results show that the proposed method reduces the command bus power consumption by 20% and 8.1% on average in the close-page and open-page policies, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.4
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• pp.252-256
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• 2006

A low-power ECC check bit generator is presented with competent DRAM implementation with minimal speed loss, area overhead and power consumption. The ECC used in the proposed scheme is a variant form of the minimum weight column code. The spatial and temporal correlations of input data are analyzed and the input paths of the check bit generator are ordered for the on-line adaptable power savings up to 24.4% in the benchmarked cases. The chip size overhead is estimated to be under 0.3% for a 80nm 1Gb DRAM implementation.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.12
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• pp.996-1002
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• 2000

Ferroelectric (Ba, Sr) TiO$_3$(BST) thin films have attracted much attention for use in new capacitor materials of dynamic random access memories (DRAMs). In order to apply BST to the DRAMs, the etching process for BST thin film with high etch rate and vertical profile must be developed. However, the former studies have the problem of low etch rate. In this study, in order to increase the etch rate, BST thin films were etched with a magnetically enhanced inductively coupled plasma(MEICP) that have much higher plasma density than RIE (reactive ion etching) and ICP (inductively coupled plasma). Experiment was done by varying the etching parameters such as CF$_4$/(CF$_4$+Ar) gas mixing ratio, rf power, dc bias voltage and chamber pressure. The maximum etch rate of the BST films was 170nm/min under CF$_4$/CF$_4$+Ar) of 0.1, 600 W/-350 V and 5 mTorr. The selectivities of BST to Pt and PR were 0.6 and 0.7, respectively. Chemical reaction and residue of the etched surface were investigated with X-ray photoelectron spectroscopy (XPS) and secondary ion mass spectroscopy (SIMS).

• Proceedings of the IEEK Conference
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• summer
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• pp.74-76
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• 2004

A Half-VDD Voltage(VHDD) Generator using PMOS pull-up transistor and NMOS pull-down transistor was newly proposed for low-voltage DRAMs. The driving current was increased and the power-on settling time was reduced in the new circuit. The newly proposed VHDD generator worked successfully at VDD at 1.5V and fabricated using 0.18um CMOS twin-well technology.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.2
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• pp.61-67
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• 2006

We fabricate local damascene FinFET cell array in sub-60nm feature sized DRAM. The local damascene structure can remove passing-gate-effects in FinFET cell array. p+ boron in-situ doped polysilicon is chosen for the gate material, and we obtain a uniform distribution of threshold voltages at around 0.7V. Sub-threshold swing of 75mV/d and extrapolated off-state leakage current of 0.03fA are obtained, which are much suppressed values against those of recessed channel array transistors. We also obtain a few times higher on-state current. Based on the improved on- and off-state current characteristics, we expect that the FinFET cell array could be a new mainstream structure in sub-60nm DRAM devices, satisfying high density, low power, and high-speed device requirements.